ADC104S051
SNAS253G–NOVEMBER2004–REVISEDMARCH2013
ADC104S0514Channel,200kspsto500ksps,10-BitA/DConverter
CheckforSamples:ADC104S051
1FEATURES
•2SpecifiedOveraRangeofSampleRates.•FourInputChannels•VariablePowerManagement•SinglePowerSupplywith2.7V-5.25VRange
APPLICATIONS
•PortableSystems•RemoteDataAcquisition•InstrumentationandControlSystems
KEYSPECIFICATIONS
•DNL:±0.13LSB(typ)•INL:+0.20/−0.10LSB(typ)•SNR:62.7dB(typ)•PowerConsumption:
–3VSupply:2.7mW(typ)–5VSupply:8.6mW(typ)
DESCRIPTION
TheADC104S051isalow-power,four-channelCMOS10-bitanalog-to-digitalconverterwithahighspeedserialinterface.Unliketheconventionalpracticeofspecifyingperformanceatasinglesamplerateonly,theADC104S051isfullyspecifiedoverasampleraterangeof200kspsto500ksps.Theconverterisbasedonaessive-approximationregisterarchitecturewithaninternaltrack-and-holdcircuit.ItcanbeconfiguredtoeptuptofourinputsignalsatinputsIN1throughIN4.
Theoutputserialdataisstraightbinary,andpatiblewithseveralstandards,suchasSPI™,QSPI™,MICROWIRE,andmonDSPserialinterfaces.
TheADC104S051operateswithasinglesupply,thatcanrangefrom+2.7Vto+5.25V.Normalpowerconsumptionusinga+3Vor+5Vsupplyis2.7mWand8.6mW,respectively.Thepower-downfeaturereducesthepowerconsumptiontojust0.12µWusinga+3Vsupply,or0.47µWusinga+5Vsupply.
TheADC104S051ispackagedina10-leadVSSOPpackage.Operationovertheindustrialtemperaturerangeof−40°Cto+85°Cisspecified.
Table1.Pin-CompatibleAlternativesbyResolutionandSpeed
(1) Resolution 12-bit10-bit8-bit 50to200kspsADC124S021ADC104S021ADC084S021 SpecifiedforSampleRateRangeof:200to500kspsADC124S051ADC104S051ADC084S051 500kspsto1MspsADC124S101ADC104S101ADC084S101
(1)Alldevicesarefullypinandpatible. ConnectionDiagram CSVAGNDIN4IN3
1 10
2 9 3ADC104S0518
4 7
5 6 SCLKDOUTDININ1IN2
1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters. Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 BlockDiagram IN1 . . MUX . IN4 T/HGND 10-BitSUCCESSIVEAPPROXIMATION ADC VAGND CONTROLLOGIC SCLKCSDINDOUT PinNo.ANALOGI/O 4-7DIGITALI/O 109 8 1POWERSUPPLY 2
3 PINDESCRIPTIONSandEQUIVALENTCIRCUITS Symbol Description IN1toIN4 Analoginputs.Thesesignalscanrangefrom0VtoVA. SCLKDOUT DINCS Digitalclockinput.Thisclockdirectlycontrolstheconversionandreadoutprocesses. Digitaldataoutput.TheoutputsamplesareclockedoutofthispinonfallingedgesoftheSCLKpin. Digitaldatainput.TheADC104S051'sControlRegisterisloadedthroughthispinonrisingedgesoftheSCLKpin. Chipselect.OnthefallingedgeofCS,aconversionprocessbegins.ConversionscontinueaslongasCSisheldlow. VAGND Positivesupplypin.Thispinshouldbeconnectedtoaquiet+2.7Vto+5.25VsourceandbypassedtoGNDwitha1µFcapacitoranda0.1µFmonolithiccapacitorlocatedwithin1cmofthepowerpin. Thegroundreturnforthesupplyandsignals. Thesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
2 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 AbsoluteMaximumRatings
(1)(2)
(3) SupplyVoltageVA VoltageonAnyPintoGNDInputCurrentatAnyPin
(4)PackageInputCurrent
(4) PowerConsumptionatTA=25°CESDSusceptibility
(6) HumanBodyModel MachineModel JunctionTemperature StorageTemperature −0.3Vto6.5V−0.3VtoVA+0.3V ±10mA±20mASee(5)2500V 250V+150°C−65°Cto+150°
C
(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seethe ElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmay degradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.
(3)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications.
(4)Whentheinputvoltageatanypinexceedsthepowersupply(thatis,VINVA),thecurrentatthatpinshouldbelimitedto10mA.The20mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepowersupplieswithan
inputcurrentof10mAtotwo.TheAbsoluteMaximumRatingspecificationdoesnotapplytotheVApin.ThecurrentintotheVApinislimitedbytheAnalogSupplyVoltagespecification.
(5)Theabsolutemaximumjunctiontemperature(TJmax)forthisdeviceis150°
C.ThemaximumallowablepowerdissipationisdictatedbyTJmax,thejunction-to-ambientthermalresistance(θJA),andtheambienttemperature(TA),andcanbecalculatedusingtheformulaPDMAX=(TJmax−TA)/θJA.Thevaluesformaximumpowerdissipationlistedabovewillbereachedonlywhenthedeviceisoperatedinaseverefaultcondition(e.g.wheninputoroutputpinsaredrivenbeyondthepowersupplyvoltages,orthepowersupplypolarityis reversed).Obviously,suchconditionsshouldalwaysbeavoided.
(6)Humanbodymodelis100pFcapacitordischargedthrougha1.5kΩresistor.Machinemodelis220pFdischargedthroughzeroohms. OperatingRatings
(1)(2) OperatingTemperatureRangeVASupplyVoltageDigitalInputPinsVoltageRangeClockFrequencyAnalogInputVoltage −40°C≤TA≤+85°C+2.7Vto+5.25V−0.3VtoVA 50kHzto16MHz0VtoVA
(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayur.OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified. PackageThermalResistance Package10-leadVSSOP θJA190°C/W Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback
3 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 ADC104S051ConverterElectricalCharacteristics
(1) ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,CL=50pF,fSCLK=3.2MHzto8MHz,fSAMPLE=200 kspsto500ksps,unlessotherwisenoted.BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°
C. Symbol Parameter Conditions Typical Limits
(2) Units STATICCONVERTERCHARACTERISTICS ResolutionwithNoMissingCodes 10 Bits INL IntegralNon-Linearity +0.2 +0.6 LSB(max) −0.1 −0.4 LSB(min) DNL DifferentialNon-Linearity ±0.13 ±0.5 LSB(max) VOFF OffsetError +0.1 ±0.5 LSB(max) OEM ChanneltoChannelOffsetErrorMatch +0.03 ±0.5 LSB(max) FSE Full-ScaleError −0.12 ±0.7 LSB(max) FSEM ChanneltoChannelFull-ScaleErrorMatch +0.02 ±0.5 LSB(max) DYNAMICCONVERTERCHARACTERISTICS SINADSignal-to-NoisePlusDistortionRatio VA=+2.7Vto5.25VfIN=40.2kHz,−0.02dBFS 61.7 61 dB(min) SNR Signal-to-NoiseRatio VA=+2.7Vto5.25VfIN=40.2kHz,−0.02dBFS 62.7 61.3 dB(min) THD TotalHarmonicDistortion VA=+2.7Vto5.25VfIN=40.2kHz,−0.02dBFS −85 −72 dB(max) SFDRSpurious-FreeDynamicRange VA=+2.7Vto5.25VfIN=40.2kHz,−0.02dBFS 84 75 dB(min) ENOBEffectiveNumberofBits VA=+2.7Vto5.25V 10 9.8 Bits(min) Channel-to-ChannelCrosstalk VA=+2.7Vto5.25V −87 dB fIN=40.2kHz IntermodulationDistortion,Second VA=5.25V −84 dB OrderTermsIMD fa=40.161kHz,fb=41.015kHz IntermodulationDistortion,ThirdOrderVA=5.25V −84 dB Terms fa=40.161kHz,fb=41.015kHz FPBW-3dBFullPowerBandwidth VA=+5VVA=+3V 11 MHz
8 MHz ANALOGINPUTCHARACTERISTICS VIN InputRange 0toVA
V IDCL DCLeakageCurrent ±
1 µA(max) CINA InputCapacitance TrackModeHoldMode 33 pF
3 pF DIGITALINPUTCHARACTERISTICS VIH InputHighVoltage VA=+5.25VVA=+3.6V 2.4 V(min) 2.1 V(min) VIL InputLowVoltage 0.8 V(max) IIN InputCurrent VIN=0VorVA ±0.01 ±10 µA(max) CIND DigitalInputCapacitance
2 4 pF(max)
(1)Min/maxspecificationlimitsarespecifiedbydesign,test,orstatisticalanalysis.
(2)TestedlimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
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(1)(continued) ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,CL=50pF,fSCLK=3.2MHzto8MHz,fSAMPLE=200 kspsto500ksps,unlessotherwisenoted.BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°
C. Symbol Parameter Conditions Typical Limits
(2) Units DIGITALOUTPUTCHARACTERISTICS VOH OutputHighVoltage ISOURCE=200µAISOURCE=1mA VA−0.03VA−0.1 VA−0.5 V(min)
V VOL OutputLowVoltage ISINK=200µAISINK=1mA 0.03 0.4 V(max) 0.1
V IOZH,IOZLTRI-STATELeakageCurrent 0.005 ±
1 µA(max) COUT TRI-STATEOutputCapacitance
2 4 pF(max) OutputCoding Straight(Natural)Binary POWERSUPPLYCHARACTERISTICS(CL=10pF) VA SupplyVoltage 2.7 V(min) 5.25 V(max) VA=+5.25V, SupplyCurrent,NormalMode fSAMPLE=500ksps,fIN=40kHz (Operational,CSlow) VA=+3.6V, fSAMPLE=500ksps,fIN=40kHzIA VA=+5.25V, SupplyCurrent,Shutdown(CShigh) fSAMPLE=0kspsVA=+3.6V, fSAMPLE=0ksps 1.64 2.1 mA(max) 0.74 0.9 mA(max) 90 nA 30 nA PowerConsumption,NormalMode VA=+5.25V (Operational,CSlow) VA=+3.6V PD PowerConsumption,Shutdown(CS VA=+5.25V high) VA=+3.6V 8.6 11 mW(max) 2.7 3.2 mW(max) 0.47 µ
W 0.11 µ
W ACELECTRICALCHARACTERISTICS fSCLK ClockFrequency See
(3) 3.2 MHz(min)
8 MHz(max) fS SampleRate See
(3) 200 ksps(min) 500 ksps(max) tCONV ConversionTime 13 SCLKcycles DC SCLKDutyCycle 30 %(min) 50 70 %(max) tACQ Track/HoldAcquisitionTime Full-ScaleStepInput
3 SCLKcycles ThroughputTime AcquisitionTime+ConversionTime 16 SCLKcycles
(3)Thisisthefrequencyrangeoverwhichtheelectricalperformanceisspecified.ThedeviceisfunctionaloverawiderrangewhichisspecifiedunderOperatingRatings. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback
5 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 ADC104S051TimingSpecifications ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,CL=50pF,fSCLK=3.2MHzto8MHz,fSAMPLE=200kspsto500ksps,,BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°
C. Symbol Parameter Conditions Typical Limits
(1) Units tCSU SetupTimeSCLKHightoCSFallingEdge See
(2) tCLH HoldtimeSCLKLowtoCSFallingEdge See
(2) tEN DelayfromCSUntilDOUTactive tACC DataessTimeafterSCLKFallingEdge tSU DataSetupTimePriortoSCLKRisingEdge tH DataValidSCLKHoldTime tCH SCLKHighPulseWidth VA=+3.0VVA=+5.0VVA=+3.0VVA=+5.0VVA=+3.0VVA=+5.0VVA=+3.0VVA=+5.0V tCL SCLKLowPulseWidth OutputFallingVA=+3.0V VA=+5.0V tDIS CSRisingEdgetoDOUTHigh-Impedance OutputRisingVA=+3.0V VA=+5.0V −3.5−0.5+4.5+1.5+4+2+16.5+15+3+3 0.5xtSCLK 0.5xtSCLK 1.71.21.01.0 10 10 30 30 10100.3xtSCLK0.3xtSCLK ns(min) ns(min) ns(max) ns(max)ns(min)ns(min)ns(min)ns(min) 20 ns(max)
(1)TestedlimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
(2)ClockmaybeeitherhighorlowwhenCSisassertedaslongassetupandholdtimestCSUandtCLHarestrictlyobserved. TimingDiagrams CSSCLK DIN Track PowerUpHold PowerDownTrack PowerUpHold 123 45678910111213141516123 45678910 Controlregisterb7b6b5b4b3b2b1b0 Controlregisterb7b6b5b4b3b2b1b0 DOUT DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0 Figure1.ADC104S051OperationalTimingDiagram DB9DB8DB7DB6DB5
6 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 Figure2.TimingTestCircuit CS tACQ tCONVERTtCH SCLK
1 2
3 4
5 6
7 8 tEN tCL tACC DOUT Z3 Z2 Z1 Z0DB9DB8DB7DB6 tSUtH DIN DONTDONTCADD2ADD1ADD0DONTCDONTCDONTC 13 14 15 16 tDIS Tri-StateDB1DB0ZeroZero Figure3.ADC104S051SerialTimingDiagram CSSCLK tCSU SCLK tCLH Figure4.SCLKandCSTimingParameters SpecificationDefinitions ACQUISITIONTIMEisthetimerequiredtoacquiretheinputvoltage.Thatis,itistimerequiredfortheholdcapacitortochargeuptotheinputvoltage. APERTUREDELAYisthetimebetweenthefourthfallingSCLKedgeofaconversionandthetimewhentheinputsignalisacquiredorheldforconversion. CONVERSIONTIMEisthetimerequired,aftertheinputvoltageisacquired,fortheADCtoconverttheinputvoltagetoadigitalword. CROSSTALKisthecouplingofenergyfromonechannelintotheotherchannel,ortheamountofsignalenergyfromoneanaloginputthatappearsatthemeasuredanaloginput. DIFFERENTIALNON-LINEARITY(DNL)isthemeasureofthemaximumdeviationfromtheidealstepsizeof1LSB. DUTYCYCLEistheratioofthetimethatarepetitivedigitalwaveformishightothetotaltimeofoneperiod.ThespecificationherereferstotheSCLK. EFFECTIVENUMBEROFBITS(ENOB,orEFFECTIVEBITS)isanothermethodofspecifyingSignal-to-NoiseandDistortionorSINAD.ENOBisdefinedas(SINAD−1.76)/6.02andsaysthattheconverterisequivalenttoaperfectADCofthis(ENOB)numberofbits. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback
7 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 FULLPOWERBANDWIDTHisameasureofthefrequencyatwhichthereconstructedoutputfundamentaldrops3dBbelowitslowfrequencyvalueforafullscaleinput. FULLSCALEERROR(FSE)isameasureofhowfarthelastcodetransitionisfromtheideal1½LSBbelow VREF+andisdefinedas: VFSE=Vmax+1.5LSB–VREF+
(1) whereVmaxisthevoltageatwhichthetransitiontothemaximumcodeurs.FSEcanbeexpressedinVolts,LSBorpercentoffullscalerange. GAINERRORisthedeviationofthelastcodetransition(111...110)to(111...111)fromtheideal(VREF−1.5LSB),afteradjustingforoffseterror. INTEGRALNON-LINEARITY(INL)isameasureofthedeviationofeachindividualcodefromalinedrawnfromnegativefullscale(½LSBbelowthefirstcodetransition)throughpositivefullscale(½LSBabovethelastcodetransition).Thedeviationofanygivencodefromthisstraightlineismeasuredfromthecenterofthatcodevalue. INTERMODULATIONDISTORTION(IMD)isthecreationofadditionalponentsasaresultoftwosinusoidalfrequenciesbeingappliedtotheADCinputatthesametime.Itisdefinedastheratioofthepowerinthesecondandthirdorderintermodulationproductstothepowerinoneoftheoriginalfrequencies.IMDisusuallyexpressedindB. MISSINGCODESarethoseoutputcodesthatwillneverappearattheADCoutputs.Thesecodescannotbereachedwithanyinputvalue.TheADC104S051isensurednottohaveanymissingcodes. OFFSETERRORisthedeviationofthefirstcodetransition(000...000)to(000...001)fromtheideal(i.e.GND+0.5LSB). SIGNALTONOISERATIO(SNR)istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofthesumofallotherponentsbelowone-halfthesamplingfrequency,notincludingd.c.ortheharmonicsincludedinTHD. SIGNALTONOISEPLUSDISTORTION(S/N+DorSINAD)Istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofalloftheotherponentsbelowhalftheclockfrequency,includingharmonicsbutexcludingd.c. SPURIOUSFREEDYNAMICRANGE(SFDR)isthedifference,expressedindB,betweenthermsvaluesoftheinputsignalandthepeakspurioussignalwhereaspurioussignalisanysignalpresentintheoutputspectrumthatisnotpresentattheinput,excludingd.c. TOTALHARMONICDISTORTION(THD)istheratio,expressedindBordBc,ofthermstotalofthefirstfiveponentsattheoutputtothermsleveloftheinputsignalfrequencyasseenattheoutput.THDiscalculatedas THD=20‡log10 Af 22 + +Af62 Af12
(2) whereAf1istheRMSpoweroftheinputfrequencyattheoutputandAf2throughAf6aretheRMSpowerinthefirst5harmonicfrequencies. THROUGHPUTTIMEistheminimumtimerequiredbetweenthestartoftwoessiveconversion.Itistheacquisitiontimeplustheconversionandreadouttimes.InthecaseoftheADC104S051,thisis16SCLKperiods.
8 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. DNL-VA=3.0V INL-VA=3.0V Figure5.DNL-VA=5.0V Figure6.INL-VA=5.0V Figure7.DNLvs.Supply Figure8.INLvs.Supply Figure9.Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 Figure10. SubmitDocumentationFeedback
9 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. DNLvs.ClockFrequency INLvs.ClockFrequency Figure11.DNLvs.ClockDutyCycle Figure12.INLvs.ClockDutyCycle Figure13.DNLvs.Temperature Figure14.INLvs.Temperature Figure15. Figure16. 10 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. SNRvs.Supply THDvs.Supply Figure17.SNRvs.ClockFrequency Figure18.THDvs.ClockFrequency Figure19.SNRvs.ClockDutyCycle Figure20.THDvs.ClockDutyCycle Figure21. Figure22. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback 11 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. SNRvs.InputFrequency THDvs.InputFrequency Figure23.SNRvs.Temperature Figure24.THDvs.Temperature Figure25.SFDRvs.Supply Figure26.SINADvs.Supply Figure27. Figure28. 12 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. SFDRvs.ClockFrequency SINADvs.ClockFrequency Figure29.SFDRvs.ClockDutyCycle Figure30.SINADvs.ClockDutyCycle Figure31.SFDRvs.InputFrequency Figure32.SINADvs.InputFrequency Figure33. Figure34. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback 13 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. SFDRvs.Temperature SINADvs.Temperature Figure35.ENOBvs.Supply Figure36.ENOBvs.ClockFrequency Figure37.ENOBvs.ClockDutyCycle Figure38.ENOBvs.InputFrequency Figure39. Figure40. 14 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. ENOBvs.Temperature SpectralResponse-3V,200ksps Figure41.SpectralResponse-5V,200ksps Figure42.SpectralResponse-3V,500ksps Figure43.SpectralResponse-5V,500ksps Figure44.PowerConsumptionvs.Throughput Figure45. Figure46. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback 15 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 APPLICATIONSINFORMATION ADC104S051OPERATION TheADC104S051isaessive-approximationanalog-to-digitalconverterdesignedaroundachargeredistributiondigital-to-analogconverter.SimplifiedschematicsoftheADC104S051inbothtrackandholdmodesareshowninFigure47Figure48,respectively.InFigure47,theADC104S051isintrackmode:switchSW1connectsthesamplingcapacitortooneoffouranaloginputchannelsthroughthemultiplexer,andSW2balancesparatorinputs.TheADC104S051isinthisstateforthefirstthreeSCLKcyclesafterCSisbroughtlow. Figure48showstheADC104S051inholdmode:switchSW1connectsthesamplingcapacitortoground,maintainingthesampledvoltage,andswitchSW2unbalancesparator.Thecontrollogictheninstructsthecharge-redistributionDACtoaddfixedamountsofchargetothesamplingcapacitoruntilparatorisbalanced.Whenparatorisbalanced,thedigitalwordsuppliedtotheDACisthedigitalrepresentationoftheanaloginputvoltage.TheADC104S051isinthisstateforthefourththroughsixteenthSCLKcyclesafterCSisbroughtlow. ThetimewhenCSislowisconsideredaserialframe.Eachoftheseframesshouldcontainanintegermultipleof16SCLKcycles,duringwhichtimeaconversionisperformedandclockedoutattheDOUTpinanddataisclockedintotheDINpintoindicatethemultiplexeraddressforthenextconversion. IN1MUX IN4SW1 SAMPLINGCAPACITOR SW2 CHARGEREDISTRIBUTION DAC + CONTROL - LOGIC AGND VA
2 Figure47.ADC104S051inTrackMode IN1MUX IN4SW1 SAMPLINGCAPACITOR SW2 CHARGEREDISTRIBUTION DAC + CONTROL - LOGIC AGND VA
2 Figure48.ADC104S051inHoldMode USINGTHEADC104S051 AnADC104S051timingdiagramandaserialinterfacetimingdiagramfortheADC104S051areshownintheTimingDiagramssection.CSischipselect,whichinitiatesconversionsandframestheserialdatatransfers.SCLK(serialclock)controlsboththeconversionprocessandthetimingofserialdata.DOUTistheserialdataoutputpin,whereaconversionresultissentasaserialdatastream,MSBfirst.DatatobewrittentotheADC104S051'sControlRegisterisplacedonDIN,theserialdatainputpin.NewdataiswrittentotheADCatDINwitheachconversion. AserialframeisinitiatedonthefallingedgeofCSandendsontherisingedgeofCS.Eachframemustcontainanintegermultipleof16risingSCLKedges.TheADCoutputdata(DOUT)isinahighimpedancestatewhenCSishighandisactivewhenCSislow.Thus,CSactsasanoutputenable.Additionally,thedevicegoesintoapowerdownstatewhenCSishigh,andalsobetweencontinuousconversioncycles. 16 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 Duringthefirst3cyclesofSCLK,theADCisinthetrackmode,acquiringtheinputvoltage.Forthenext13SCLKcyclestheconversionisplishedandthedataisclockedout,MSBfirst,startingonthe5thclock.Ifthereismorethanoneconversioninaframe,theADCwillre-enterthetrackmodeonthefallingedgeofSCLKaftertheN*16thrisingedgeofSCLK,andre-enterthehold/convertmodeontheN*16+4thfallingedgeofSCLK,where"N"isaninteger. WhenCSisbroughthigh,SCLKisinternallygatedoff.IfSCLKispedinthelowstatewhileCSishigh,thesubsequentfallofCSwillgenerateafallingedgeoftheinternalversionofSCLK,puttingtheADCintothetrackmode.ThisisseenbytheADCasthefirstfallingedgeofSCLK.IfSCLKispedwithSCLKhigh,theADCentersthetrackmodeonthefirstfallingedgeofSCLKafterthefallingedgeofCS. Duringeachconversion,dataisclockedintotheDINpinonthefirst8risingedgesofSCLKafterthefallofCS.Foreachconversion,itisnecessarytoclockinthedataindicatingtheinputthatisselectedfortheconversionafterthecurrentone.SeeTable2Table3andTable4. IfCSandSCLKgolowwithinthetimesdefinedbytCSUandtCLH,therisingedgeofSCLKthatbeginsclockingdatainatDINmaybeoneclockcyclelaterthanexpected.Itis,therefore,besttostrictlyobservetheminimumtCSUandtCLHtimesgivenintheTimingSpecifications. Therearenopower-updelaysordummyconversionsrequiredwiththeADC104S051.TheADCisabletosampleandconvertaninputtofullconversionimmediatelyfollowingpowerup.Thefirstconversionresultafterpower-upwillbethatofIN1. Bit7(MSB)DONTC Bit6DONTC Bit5ADD2 Table2.ControlRegisterBits Bit4ADD1 Bit3ADD0 Bit2DONTC Bit1DONTC Bit0DONTC Bit#:7-6,2-0543 Symbol:DONTCADD2ADD1ADD0 Table3.ControlRegisterBitDescriptions DescriptionDon'tcare.Thevalueofthesebitsdonotaffectdeviceoperation.Thesethreebitsdeterminewhichinputchannelwillbesampledandconvertedinthenexttrack/holdcycle.ThemappingbetweencodesandchannelsisshowninTable4. ADD2xxxx Table4.InputChannelSelection ADD10011 ADD00101 InputChannelIN1(Default) IN2IN3IN4 ADC104S051TRANSFERFUNCTION TheoutputformatoftheADC104S051isstraightbinary.CodetransitionsurmidwaybetweenessiveintegerLSBvalues.TheLSBwidthfortheADC104S051isVA/1024.TheidealtransfercharacteristicisshowninFigure49.Thetransitionfromanoutputcodeof0000000000toacodeof0000000001isat1/2LSB,oravoltageofVA/2048.OthercodetransitionsuratstepsofoneLSB. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback 17 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 111...111111...110 111...000 | 011...111 | 1LSB=VA/1024 ADCCODE 000...010000...001000...000 0V0.5LSB | ANALOGINPUT+VA-1.5LSB Figure49.IdealTransferCharacteristic TYPICALAPPLICATIONCIRCUIT AtypicalapplicationoftheADC104S051isshowninFigure50.PowerisprovidedinthisexamplebytheTexasInstrumentsLP2950low-dropoutvoltageregulator,availableinavarietyoffixedandadjustableoutputvoltages.ThepowersupplypinisbypassedwithaworklocatedclosetotheADC104S051. BecausethereferencefortheADC104S051isthesupplyvoltage,anynoiseonthesupplywilldegradedevicenoiseperformance.Tokeepnoiseoffthesupply,useadedicatedlinearregulatorforthisdevice,orprovidesufficientdecouplingfromothercircuitrytokeepnoiseofftheADC104S051supplypin.BecauseoftheADC104S051'slowpowerrequirements,itisalsopossibletouseaprecisionreferenceasapowersupplytomaximizeperformance.Thefour-wireinterfaceisalsoshownconnectedtoamicroprocessororDSP. 1PFTANT LP29500.1PF 1PF 5V0.1PF VA IN1 SCLK IN2ADC104S051CS IN3 DIN IN4 DOUT GND MICROPROCESSORDSP Figure50.TypicalApplicationCircuit ANALOGINPUTS AnequivalentcircuitforoneoftheADC104S051'sinputchannelsisshowninFigure51.DiodesD1andD2provideESDprotectionfortheanaloginputs.Atnotimeshouldanyinputgobeyond(VA+300mV)or(GND−300mV),astheseESDdiodeswillbeginconducting,whichcouldresultinerraticoperation.Forthisreason,theseESDdiodesshouldNOTbeusedtoclamptheinputsignal. ThecapacitorC1inFigure51hasatypicalvalueof3pF,andismainlythepackagepincapacitance.ResistorR1istheonresistanceofthemultiplexerandtrack/holdswitch,andistypically500ohms.CapacitorC2istheADC104S051samplingcapacitor,andistypically30pF.TheADC104S051willdeliverbestperformancewhendrivenbyalow-impedancesourcetoeliminatedistortioncausedbythechargingofthesamplingcapacitance.ThisisespeciallyimportantwhenusingtheADC104S051tosampleACsignals.Alsoimportantwhensamplingdynamicsignalsisaband-passorlow-passfiltertoreduceharmonicsandnoise,improvingdynamicperformance. 18 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 VA VINC13pF D1 C2 R130pF D2 ConversionPhase-SwitchOpenTrackPhase-SwitchClosed Figure51.EquivalentInputCircuit DIGITALINPUTSANDOUTPUTS TheADC104S051'sdigitaloutputDOUTislimitedby,andcannotexceed,thesupplyvoltage,VA.Thedigitalinputpinsarenotpronetolatch-upand,andalthoughnotmended,SCLK,CSandDINmaybeassertedbeforeVAwithoutanylatchuprisk. POWERSUPPLYCONSIDERATIONS TheADC104S051isfullypowered-upwheneverCSislow,andfullypowered-downwheneverCSishigh,withoneexception:theADC104S051automaticallyenterspower-downmodebetweenthe16thfallingedgeofaconversionandthe1stfallingedgeofthesubsequentconversion(seeTimingDiagrams). TheADC104S051canperformmultipleconversionsbacktoback;eachconversionrequires16SCLKcycles.TheADC104S051willperformconversionscontinuouslyaslongasCSisheldlow. Theusermaytradeoffthroughputforpowerconsumptionbysimplyperformingfewerconversionsperunittime.ThePowerConsumptionvs.SampleRatecurveintheTypicalPerformanceCharacteristicssectionshowsthetypicalpowerconsumptionoftheADC104S051versusthroughput.Tocalculatethepowerconsumption,simplymultiplythefractionoftimespentinthenormalmodebythenormalmodepowerconsumption,andaddthefractionoftimespentinshutdownmodemultipliedbytheshutdownmodepowerdissipation. PowerManagement WhentheADC104S051isoperatedcontinuouslyinnormalmode,themaximumthroughputisfSCLK/16.ThroughputmaybetradedforpowerconsumptionbyrunningfSCLKatitsmaximum8MHzandperformingfewerconversionsperunittime,puttingtheADC104S051intoshutdownmodebetweenconversions.AplotoftypicalpowerconsumptionversusthroughputisshownintheTypicalPerformanceCharacteristicssection.Tocalculatethepowerconsumptionforagiventhroughput,multiplythefractionoftimespentinthenormalmodebythenormalmodepowerconsumptionandaddthefractionoftimespentinshutdownmodemultipliedbytheshutdownmodepowerconsumption.Generally,theuserwillputthepartintonormalmodeandthenputthepartbackintoshutdownmode.Notethatthecurveofpowerconsumptionvs.throughputisnearlylinear.Thisisbecausethepowerconsumptionintheshutdownmodeissosmallthatitcanbeignoredforallpracticalpurposes. PowerSupplyNoiseConsiderations Thechargingofanyoutputloadcapacitancerequirescurrentfromthepowersupply,VA.Thecurrentpulsesrequiredfromthesupplytochargetheoutputcapacitancewillcausevoltagevariationsonthesupply.Ifthesevariationsarelargeenough,theycoulddegradeSNRandSINADperformanceoftheADC.Furthermore,dischargingtheoutputcapacitancewhenthedigitaloutputgoesfromalogichightoalogiclowwilldumpcurrentintothediesubstrate,whichisresistive.Loaddischargecurrentswillcause"groundbounce"noiseinthesubstratethatwilldegradenoiseperformanceifthatcurrentislargeenough.Thelargeristheoutputcapacitance,themorecurrentflowsthroughthediesubstrateandthegreateristhenoisecoupledintotheanalogchannel,degradingnoiseperformance. Tokeepnoiseoutofthepowersupply,keeptheoutputloadcapacitanceassmallaspractical.Iftheloadcapacitanceisgreaterthan50pF,usea100ΩseriesresistorattheADCoutput,locatedasclosetotheADCoutputpinaspractical.Thiswilllimitthechargeanddischargecurrentoftheoutputcapacitanceandimprovenoiseperformance. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback 19 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013REVISIONHISTORY ChangesfromRevisionF(March2013)toRevisionG Page •ChangedlayoutofNationalDataSheettoTIformat
(1) ACTIVE PackageTypePackageDrawing VSSOP DGS PinsPackageQty 101000 EcoPlan
(2) Green(RoHS&noSb/Br) Lead/BallFinish
(6) CUSN MSLPeakTemp
(3) Level-1-260C-UNLIM OpTemp(°C)-40to85
(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicemendedfornewdesigns.LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.NRND:Notmendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotmendusingthispartinanewdesign.PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. DeviceMarking (4/5) X11C
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatpliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.TImayreferencethesetypesofproductsas"Pb-Free".RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutpliantwithEURoHSpursuanttoaspecificEURoHSexemption.Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.-TheMoistureSensitivityLevelratingordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.IfalineisindentedthenitisacontinuationofthepreviouslineandthebinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Lead/BallFinish-OrderableDevicesmayhavemultiplematerialfinishoptions.Finishoptionsareseparatedbyaverticalruledline.Lead/BallFinishvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth. ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisoningmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis. Samples Addendum-Page1 TAPEANDREELINFORMATION PACKAGEMATERIALSINFORMATION 24-Aug-2017 *AlldimensionsarenominalDevice PackagePackageTypeDrawing Pins ADC104S051CIMM/NOPBVSSOPDGS10 SPQ1000 ReelReelDiameterWidth (mm)W1(mm) 178.012.4 A0(mm) 5.3 B0(mm) 3.4 K0(mm) 1.4 P1(mm) 8.0
W Pin1 (mm)Quadrant 12.0 Q1 PackMaterials-Page1 PACKAGEMATERIALSINFORMATION 24-Aug-2017 *AlldimensionsarenominalDevice ADC104S051CIMM/NOPB PackageTypeVSSOP PackageDrawingPins DGS 10 SPQ1000 Length(mm)210.0 Width(mm)185.0 Height(mm)35.0 PackMaterials-Page2 IMPORTANTNOTICE TexasInstrumentsIncorporated(TI)reservestherighttomakecorrections,enhancements,improvementsandotherchangestoitssemiconductorproductsandservicesperJESD46,latestissue,andtodiscontinueanyproductorserviceperJESD48,latestissue.Buyersshouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentplete. TI’spublishedtermsofsaleforsemiconductorproducts()applytothesaleofpackagedintegratedcircuitproductsthatTIhasqualifiedandreleasedtomarket.AdditionaltermsmayapplytotheuseorsaleofothertypesofTIproductsandservices. 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DesignerwillfullyindemnifyTIanditsrepresentativesagainstanydamages,costs,losses,and/orliabilitiesarisingoutofDesigner’spliancewiththetermsandprovisionsofthisNotice. MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265Copyright©2017,TexasInstrumentsIncorporated
(1) Resolution 12-bit10-bit8-bit 50to200kspsADC124S021ADC104S021ADC084S021 SpecifiedforSampleRateRangeof:200to500kspsADC124S051ADC104S051ADC084S051 500kspsto1MspsADC124S101ADC104S101ADC084S101
(1)Alldevicesarefullypinandpatible. ConnectionDiagram CSVAGNDIN4IN3
1 10
2 9 3ADC104S0518
4 7
5 6 SCLKDOUTDININ1IN2
1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters. Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 BlockDiagram IN1 . . MUX . IN4 T/HGND 10-BitSUCCESSIVEAPPROXIMATION ADC VAGND CONTROLLOGIC SCLKCSDINDOUT PinNo.ANALOGI/O 4-7DIGITALI/O 109 8 1POWERSUPPLY 2
3 PINDESCRIPTIONSandEQUIVALENTCIRCUITS Symbol Description IN1toIN4 Analoginputs.Thesesignalscanrangefrom0VtoVA. SCLKDOUT DINCS Digitalclockinput.Thisclockdirectlycontrolstheconversionandreadoutprocesses. Digitaldataoutput.TheoutputsamplesareclockedoutofthispinonfallingedgesoftheSCLKpin. Digitaldatainput.TheADC104S051'sControlRegisterisloadedthroughthispinonrisingedgesoftheSCLKpin. Chipselect.OnthefallingedgeofCS,aconversionprocessbegins.ConversionscontinueaslongasCSisheldlow. VAGND Positivesupplypin.Thispinshouldbeconnectedtoaquiet+2.7Vto+5.25VsourceandbypassedtoGNDwitha1µFcapacitoranda0.1µFmonolithiccapacitorlocatedwithin1cmofthepowerpin. Thegroundreturnforthesupplyandsignals. Thesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
2 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 AbsoluteMaximumRatings
(1)(2)
(3) SupplyVoltageVA VoltageonAnyPintoGNDInputCurrentatAnyPin
(4)PackageInputCurrent
(4) PowerConsumptionatTA=25°CESDSusceptibility
(6) HumanBodyModel MachineModel JunctionTemperature StorageTemperature −0.3Vto6.5V−0.3VtoVA+0.3V ±10mA±20mASee(5)2500V 250V+150°C−65°Cto+150°
C
(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seethe ElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmay degradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.
(3)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications.
(4)Whentheinputvoltageatanypinexceedsthepowersupply(thatis,VIN
(5)Theabsolutemaximumjunctiontemperature(TJmax)forthisdeviceis150°
C.ThemaximumallowablepowerdissipationisdictatedbyTJmax,thejunction-to-ambientthermalresistance(θJA),andtheambienttemperature(TA),andcanbecalculatedusingtheformulaPDMAX=(TJmax−TA)/θJA.Thevaluesformaximumpowerdissipationlistedabovewillbereachedonlywhenthedeviceisoperatedinaseverefaultcondition(e.g.wheninputoroutputpinsaredrivenbeyondthepowersupplyvoltages,orthepowersupplypolarityis reversed).Obviously,suchconditionsshouldalwaysbeavoided.
(6)Humanbodymodelis100pFcapacitordischargedthrougha1.5kΩresistor.Machinemodelis220pFdischargedthroughzeroohms. OperatingRatings
(1)(2) OperatingTemperatureRangeVASupplyVoltageDigitalInputPinsVoltageRangeClockFrequencyAnalogInputVoltage −40°C≤TA≤+85°C+2.7Vto+5.25V−0.3VtoVA 50kHzto16MHz0VtoVA
(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayur.OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified. PackageThermalResistance Package10-leadVSSOP θJA190°C/W Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback
3 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 ADC104S051ConverterElectricalCharacteristics
(1) ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,CL=50pF,fSCLK=3.2MHzto8MHz,fSAMPLE=200 kspsto500ksps,unlessotherwisenoted.BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°
C. Symbol Parameter Conditions Typical Limits
(2) Units STATICCONVERTERCHARACTERISTICS ResolutionwithNoMissingCodes 10 Bits INL IntegralNon-Linearity +0.2 +0.6 LSB(max) −0.1 −0.4 LSB(min) DNL DifferentialNon-Linearity ±0.13 ±0.5 LSB(max) VOFF OffsetError +0.1 ±0.5 LSB(max) OEM ChanneltoChannelOffsetErrorMatch +0.03 ±0.5 LSB(max) FSE Full-ScaleError −0.12 ±0.7 LSB(max) FSEM ChanneltoChannelFull-ScaleErrorMatch +0.02 ±0.5 LSB(max) DYNAMICCONVERTERCHARACTERISTICS SINADSignal-to-NoisePlusDistortionRatio VA=+2.7Vto5.25VfIN=40.2kHz,−0.02dBFS 61.7 61 dB(min) SNR Signal-to-NoiseRatio VA=+2.7Vto5.25VfIN=40.2kHz,−0.02dBFS 62.7 61.3 dB(min) THD TotalHarmonicDistortion VA=+2.7Vto5.25VfIN=40.2kHz,−0.02dBFS −85 −72 dB(max) SFDRSpurious-FreeDynamicRange VA=+2.7Vto5.25VfIN=40.2kHz,−0.02dBFS 84 75 dB(min) ENOBEffectiveNumberofBits VA=+2.7Vto5.25V 10 9.8 Bits(min) Channel-to-ChannelCrosstalk VA=+2.7Vto5.25V −87 dB fIN=40.2kHz IntermodulationDistortion,Second VA=5.25V −84 dB OrderTermsIMD fa=40.161kHz,fb=41.015kHz IntermodulationDistortion,ThirdOrderVA=5.25V −84 dB Terms fa=40.161kHz,fb=41.015kHz FPBW-3dBFullPowerBandwidth VA=+5VVA=+3V 11 MHz
8 MHz ANALOGINPUTCHARACTERISTICS VIN InputRange 0toVA
V IDCL DCLeakageCurrent ±
1 µA(max) CINA InputCapacitance TrackModeHoldMode 33 pF
3 pF DIGITALINPUTCHARACTERISTICS VIH InputHighVoltage VA=+5.25VVA=+3.6V 2.4 V(min) 2.1 V(min) VIL InputLowVoltage 0.8 V(max) IIN InputCurrent VIN=0VorVA ±0.01 ±10 µA(max) CIND DigitalInputCapacitance
2 4 pF(max)
(1)Min/maxspecificationlimitsarespecifiedbydesign,test,orstatisticalanalysis.
(2)TestedlimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
4 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 ADC104S051ConverterElectricalCharacteristics
(1)(continued) ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,CL=50pF,fSCLK=3.2MHzto8MHz,fSAMPLE=200 kspsto500ksps,unlessotherwisenoted.BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°
C. Symbol Parameter Conditions Typical Limits
(2) Units DIGITALOUTPUTCHARACTERISTICS VOH OutputHighVoltage ISOURCE=200µAISOURCE=1mA VA−0.03VA−0.1 VA−0.5 V(min)
V VOL OutputLowVoltage ISINK=200µAISINK=1mA 0.03 0.4 V(max) 0.1
V IOZH,IOZLTRI-STATELeakageCurrent 0.005 ±
1 µA(max) COUT TRI-STATEOutputCapacitance
2 4 pF(max) OutputCoding Straight(Natural)Binary POWERSUPPLYCHARACTERISTICS(CL=10pF) VA SupplyVoltage 2.7 V(min) 5.25 V(max) VA=+5.25V, SupplyCurrent,NormalMode fSAMPLE=500ksps,fIN=40kHz (Operational,CSlow) VA=+3.6V, fSAMPLE=500ksps,fIN=40kHzIA VA=+5.25V, SupplyCurrent,Shutdown(CShigh) fSAMPLE=0kspsVA=+3.6V, fSAMPLE=0ksps 1.64 2.1 mA(max) 0.74 0.9 mA(max) 90 nA 30 nA PowerConsumption,NormalMode VA=+5.25V (Operational,CSlow) VA=+3.6V PD PowerConsumption,Shutdown(CS VA=+5.25V high) VA=+3.6V 8.6 11 mW(max) 2.7 3.2 mW(max) 0.47 µ
W 0.11 µ
W ACELECTRICALCHARACTERISTICS fSCLK ClockFrequency See
(3) 3.2 MHz(min)
8 MHz(max) fS SampleRate See
(3) 200 ksps(min) 500 ksps(max) tCONV ConversionTime 13 SCLKcycles DC SCLKDutyCycle 30 %(min) 50 70 %(max) tACQ Track/HoldAcquisitionTime Full-ScaleStepInput
3 SCLKcycles ThroughputTime AcquisitionTime+ConversionTime 16 SCLKcycles
(3)Thisisthefrequencyrangeoverwhichtheelectricalperformanceisspecified.ThedeviceisfunctionaloverawiderrangewhichisspecifiedunderOperatingRatings. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback
5 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 ADC104S051TimingSpecifications ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,CL=50pF,fSCLK=3.2MHzto8MHz,fSAMPLE=200kspsto500ksps,,BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°
C. Symbol Parameter Conditions Typical Limits
(1) Units tCSU SetupTimeSCLKHightoCSFallingEdge See
(2) tCLH HoldtimeSCLKLowtoCSFallingEdge See
(2) tEN DelayfromCSUntilDOUTactive tACC DataessTimeafterSCLKFallingEdge tSU DataSetupTimePriortoSCLKRisingEdge tH DataValidSCLKHoldTime tCH SCLKHighPulseWidth VA=+3.0VVA=+5.0VVA=+3.0VVA=+5.0VVA=+3.0VVA=+5.0VVA=+3.0VVA=+5.0V tCL SCLKLowPulseWidth OutputFallingVA=+3.0V VA=+5.0V tDIS CSRisingEdgetoDOUTHigh-Impedance OutputRisingVA=+3.0V VA=+5.0V −3.5−0.5+4.5+1.5+4+2+16.5+15+3+3 0.5xtSCLK 0.5xtSCLK 1.71.21.01.0 10 10 30 30 10100.3xtSCLK0.3xtSCLK ns(min) ns(min) ns(max) ns(max)ns(min)ns(min)ns(min)ns(min) 20 ns(max)
(1)TestedlimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
(2)ClockmaybeeitherhighorlowwhenCSisassertedaslongassetupandholdtimestCSUandtCLHarestrictlyobserved. TimingDiagrams CSSCLK DIN Track PowerUpHold PowerDownTrack PowerUpHold 123 45678910111213141516123 45678910 Controlregisterb7b6b5b4b3b2b1b0 Controlregisterb7b6b5b4b3b2b1b0 DOUT DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0 Figure1.ADC104S051OperationalTimingDiagram DB9DB8DB7DB6DB5
6 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 Figure2.TimingTestCircuit CS tACQ tCONVERTtCH SCLK
1 2
3 4
5 6
7 8 tEN tCL tACC DOUT Z3 Z2 Z1 Z0DB9DB8DB7DB6 tSUtH DIN DONTDONTCADD2ADD1ADD0DONTCDONTCDONTC 13 14 15 16 tDIS Tri-StateDB1DB0ZeroZero Figure3.ADC104S051SerialTimingDiagram CSSCLK tCSU SCLK tCLH Figure4.SCLKandCSTimingParameters SpecificationDefinitions ACQUISITIONTIMEisthetimerequiredtoacquiretheinputvoltage.Thatis,itistimerequiredfortheholdcapacitortochargeuptotheinputvoltage. APERTUREDELAYisthetimebetweenthefourthfallingSCLKedgeofaconversionandthetimewhentheinputsignalisacquiredorheldforconversion. CONVERSIONTIMEisthetimerequired,aftertheinputvoltageisacquired,fortheADCtoconverttheinputvoltagetoadigitalword. CROSSTALKisthecouplingofenergyfromonechannelintotheotherchannel,ortheamountofsignalenergyfromoneanaloginputthatappearsatthemeasuredanaloginput. DIFFERENTIALNON-LINEARITY(DNL)isthemeasureofthemaximumdeviationfromtheidealstepsizeof1LSB. DUTYCYCLEistheratioofthetimethatarepetitivedigitalwaveformishightothetotaltimeofoneperiod.ThespecificationherereferstotheSCLK. EFFECTIVENUMBEROFBITS(ENOB,orEFFECTIVEBITS)isanothermethodofspecifyingSignal-to-NoiseandDistortionorSINAD.ENOBisdefinedas(SINAD−1.76)/6.02andsaysthattheconverterisequivalenttoaperfectADCofthis(ENOB)numberofbits. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback
7 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 FULLPOWERBANDWIDTHisameasureofthefrequencyatwhichthereconstructedoutputfundamentaldrops3dBbelowitslowfrequencyvalueforafullscaleinput. FULLSCALEERROR(FSE)isameasureofhowfarthelastcodetransitionisfromtheideal1½LSBbelow VREF+andisdefinedas: VFSE=Vmax+1.5LSB–VREF+
(1) whereVmaxisthevoltageatwhichthetransitiontothemaximumcodeurs.FSEcanbeexpressedinVolts,LSBorpercentoffullscalerange. GAINERRORisthedeviationofthelastcodetransition(111...110)to(111...111)fromtheideal(VREF−1.5LSB),afteradjustingforoffseterror. INTEGRALNON-LINEARITY(INL)isameasureofthedeviationofeachindividualcodefromalinedrawnfromnegativefullscale(½LSBbelowthefirstcodetransition)throughpositivefullscale(½LSBabovethelastcodetransition).Thedeviationofanygivencodefromthisstraightlineismeasuredfromthecenterofthatcodevalue. INTERMODULATIONDISTORTION(IMD)isthecreationofadditionalponentsasaresultoftwosinusoidalfrequenciesbeingappliedtotheADCinputatthesametime.Itisdefinedastheratioofthepowerinthesecondandthirdorderintermodulationproductstothepowerinoneoftheoriginalfrequencies.IMDisusuallyexpressedindB. MISSINGCODESarethoseoutputcodesthatwillneverappearattheADCoutputs.Thesecodescannotbereachedwithanyinputvalue.TheADC104S051isensurednottohaveanymissingcodes. OFFSETERRORisthedeviationofthefirstcodetransition(000...000)to(000...001)fromtheideal(i.e.GND+0.5LSB). SIGNALTONOISERATIO(SNR)istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofthesumofallotherponentsbelowone-halfthesamplingfrequency,notincludingd.c.ortheharmonicsincludedinTHD. SIGNALTONOISEPLUSDISTORTION(S/N+DorSINAD)Istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofalloftheotherponentsbelowhalftheclockfrequency,includingharmonicsbutexcludingd.c. SPURIOUSFREEDYNAMICRANGE(SFDR)isthedifference,expressedindB,betweenthermsvaluesoftheinputsignalandthepeakspurioussignalwhereaspurioussignalisanysignalpresentintheoutputspectrumthatisnotpresentattheinput,excludingd.c. TOTALHARMONICDISTORTION(THD)istheratio,expressedindBordBc,ofthermstotalofthefirstfiveponentsattheoutputtothermsleveloftheinputsignalfrequencyasseenattheoutput.THDiscalculatedas THD=20‡log10 Af 22 + +Af62 Af12
(2) whereAf1istheRMSpoweroftheinputfrequencyattheoutputandAf2throughAf6aretheRMSpowerinthefirst5harmonicfrequencies. THROUGHPUTTIMEistheminimumtimerequiredbetweenthestartoftwoessiveconversion.Itistheacquisitiontimeplustheconversionandreadouttimes.InthecaseoftheADC104S051,thisis16SCLKperiods.
8 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. DNL-VA=3.0V INL-VA=3.0V Figure5.DNL-VA=5.0V Figure6.INL-VA=5.0V Figure7.DNLvs.Supply Figure8.INLvs.Supply Figure9.Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 Figure10. SubmitDocumentationFeedback
9 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. DNLvs.ClockFrequency INLvs.ClockFrequency Figure11.DNLvs.ClockDutyCycle Figure12.INLvs.ClockDutyCycle Figure13.DNLvs.Temperature Figure14.INLvs.Temperature Figure15. Figure16. 10 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. SNRvs.Supply THDvs.Supply Figure17.SNRvs.ClockFrequency Figure18.THDvs.ClockFrequency Figure19.SNRvs.ClockDutyCycle Figure20.THDvs.ClockDutyCycle Figure21. Figure22. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback 11 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. SNRvs.InputFrequency THDvs.InputFrequency Figure23.SNRvs.Temperature Figure24.THDvs.Temperature Figure25.SFDRvs.Supply Figure26.SINADvs.Supply Figure27. Figure28. 12 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. SFDRvs.ClockFrequency SINADvs.ClockFrequency Figure29.SFDRvs.ClockDutyCycle Figure30.SINADvs.ClockDutyCycle Figure31.SFDRvs.InputFrequency Figure32.SINADvs.InputFrequency Figure33. Figure34. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback 13 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. SFDRvs.Temperature SINADvs.Temperature Figure35.ENOBvs.Supply Figure36.ENOBvs.ClockFrequency Figure37.ENOBvs.ClockDutyCycle Figure38.ENOBvs.InputFrequency Figure39. Figure40. 14 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 TypicalPerformanceCharacteristics(continued) TA=+25°C,fSAMPLE=200kspsto500ksps,fSCLK=3.2MHzto8MHz,fIN=40.2kHzunlessotherwisestated. ENOBvs.Temperature SpectralResponse-3V,200ksps Figure41.SpectralResponse-5V,200ksps Figure42.SpectralResponse-3V,500ksps Figure43.SpectralResponse-5V,500ksps Figure44.PowerConsumptionvs.Throughput Figure45. Figure46. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback 15 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 APPLICATIONSINFORMATION ADC104S051OPERATION TheADC104S051isaessive-approximationanalog-to-digitalconverterdesignedaroundachargeredistributiondigital-to-analogconverter.SimplifiedschematicsoftheADC104S051inbothtrackandholdmodesareshowninFigure47Figure48,respectively.InFigure47,theADC104S051isintrackmode:switchSW1connectsthesamplingcapacitortooneoffouranaloginputchannelsthroughthemultiplexer,andSW2balancesparatorinputs.TheADC104S051isinthisstateforthefirstthreeSCLKcyclesafterCSisbroughtlow. Figure48showstheADC104S051inholdmode:switchSW1connectsthesamplingcapacitortoground,maintainingthesampledvoltage,andswitchSW2unbalancesparator.Thecontrollogictheninstructsthecharge-redistributionDACtoaddfixedamountsofchargetothesamplingcapacitoruntilparatorisbalanced.Whenparatorisbalanced,thedigitalwordsuppliedtotheDACisthedigitalrepresentationoftheanaloginputvoltage.TheADC104S051isinthisstateforthefourththroughsixteenthSCLKcyclesafterCSisbroughtlow. ThetimewhenCSislowisconsideredaserialframe.Eachoftheseframesshouldcontainanintegermultipleof16SCLKcycles,duringwhichtimeaconversionisperformedandclockedoutattheDOUTpinanddataisclockedintotheDINpintoindicatethemultiplexeraddressforthenextconversion. IN1MUX IN4SW1 SAMPLINGCAPACITOR SW2 CHARGEREDISTRIBUTION DAC + CONTROL - LOGIC AGND VA
2 Figure47.ADC104S051inTrackMode IN1MUX IN4SW1 SAMPLINGCAPACITOR SW2 CHARGEREDISTRIBUTION DAC + CONTROL - LOGIC AGND VA
2 Figure48.ADC104S051inHoldMode USINGTHEADC104S051 AnADC104S051timingdiagramandaserialinterfacetimingdiagramfortheADC104S051areshownintheTimingDiagramssection.CSischipselect,whichinitiatesconversionsandframestheserialdatatransfers.SCLK(serialclock)controlsboththeconversionprocessandthetimingofserialdata.DOUTistheserialdataoutputpin,whereaconversionresultissentasaserialdatastream,MSBfirst.DatatobewrittentotheADC104S051'sControlRegisterisplacedonDIN,theserialdatainputpin.NewdataiswrittentotheADCatDINwitheachconversion. AserialframeisinitiatedonthefallingedgeofCSandendsontherisingedgeofCS.Eachframemustcontainanintegermultipleof16risingSCLKedges.TheADCoutputdata(DOUT)isinahighimpedancestatewhenCSishighandisactivewhenCSislow.Thus,CSactsasanoutputenable.Additionally,thedevicegoesintoapowerdownstatewhenCSishigh,andalsobetweencontinuousconversioncycles. 16 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 Duringthefirst3cyclesofSCLK,theADCisinthetrackmode,acquiringtheinputvoltage.Forthenext13SCLKcyclestheconversionisplishedandthedataisclockedout,MSBfirst,startingonthe5thclock.Ifthereismorethanoneconversioninaframe,theADCwillre-enterthetrackmodeonthefallingedgeofSCLKaftertheN*16thrisingedgeofSCLK,andre-enterthehold/convertmodeontheN*16+4thfallingedgeofSCLK,where"N"isaninteger. WhenCSisbroughthigh,SCLKisinternallygatedoff.IfSCLKispedinthelowstatewhileCSishigh,thesubsequentfallofCSwillgenerateafallingedgeoftheinternalversionofSCLK,puttingtheADCintothetrackmode.ThisisseenbytheADCasthefirstfallingedgeofSCLK.IfSCLKispedwithSCLKhigh,theADCentersthetrackmodeonthefirstfallingedgeofSCLKafterthefallingedgeofCS. Duringeachconversion,dataisclockedintotheDINpinonthefirst8risingedgesofSCLKafterthefallofCS.Foreachconversion,itisnecessarytoclockinthedataindicatingtheinputthatisselectedfortheconversionafterthecurrentone.SeeTable2Table3andTable4. IfCSandSCLKgolowwithinthetimesdefinedbytCSUandtCLH,therisingedgeofSCLKthatbeginsclockingdatainatDINmaybeoneclockcyclelaterthanexpected.Itis,therefore,besttostrictlyobservetheminimumtCSUandtCLHtimesgivenintheTimingSpecifications. Therearenopower-updelaysordummyconversionsrequiredwiththeADC104S051.TheADCisabletosampleandconvertaninputtofullconversionimmediatelyfollowingpowerup.Thefirstconversionresultafterpower-upwillbethatofIN1. Bit7(MSB)DONTC Bit6DONTC Bit5ADD2 Table2.ControlRegisterBits Bit4ADD1 Bit3ADD0 Bit2DONTC Bit1DONTC Bit0DONTC Bit#:7-6,2-0543 Symbol:DONTCADD2ADD1ADD0 Table3.ControlRegisterBitDescriptions DescriptionDon'tcare.Thevalueofthesebitsdonotaffectdeviceoperation.Thesethreebitsdeterminewhichinputchannelwillbesampledandconvertedinthenexttrack/holdcycle.ThemappingbetweencodesandchannelsisshowninTable4. ADD2xxxx Table4.InputChannelSelection ADD10011 ADD00101 InputChannelIN1(Default) IN2IN3IN4 ADC104S051TRANSFERFUNCTION TheoutputformatoftheADC104S051isstraightbinary.CodetransitionsurmidwaybetweenessiveintegerLSBvalues.TheLSBwidthfortheADC104S051isVA/1024.TheidealtransfercharacteristicisshowninFigure49.Thetransitionfromanoutputcodeof0000000000toacodeof0000000001isat1/2LSB,oravoltageofVA/2048.OthercodetransitionsuratstepsofoneLSB. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback 17 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 111...111111...110 111...000 | 011...111 | 1LSB=VA/1024 ADCCODE 000...010000...001000...000 0V0.5LSB | ANALOGINPUT+VA-1.5LSB Figure49.IdealTransferCharacteristic TYPICALAPPLICATIONCIRCUIT AtypicalapplicationoftheADC104S051isshowninFigure50.PowerisprovidedinthisexamplebytheTexasInstrumentsLP2950low-dropoutvoltageregulator,availableinavarietyoffixedandadjustableoutputvoltages.ThepowersupplypinisbypassedwithaworklocatedclosetotheADC104S051. BecausethereferencefortheADC104S051isthesupplyvoltage,anynoiseonthesupplywilldegradedevicenoiseperformance.Tokeepnoiseoffthesupply,useadedicatedlinearregulatorforthisdevice,orprovidesufficientdecouplingfromothercircuitrytokeepnoiseofftheADC104S051supplypin.BecauseoftheADC104S051'slowpowerrequirements,itisalsopossibletouseaprecisionreferenceasapowersupplytomaximizeperformance.Thefour-wireinterfaceisalsoshownconnectedtoamicroprocessororDSP. 1PFTANT LP29500.1PF 1PF 5V0.1PF VA IN1 SCLK IN2ADC104S051CS IN3 DIN IN4 DOUT GND MICROPROCESSORDSP Figure50.TypicalApplicationCircuit ANALOGINPUTS AnequivalentcircuitforoneoftheADC104S051'sinputchannelsisshowninFigure51.DiodesD1andD2provideESDprotectionfortheanaloginputs.Atnotimeshouldanyinputgobeyond(VA+300mV)or(GND−300mV),astheseESDdiodeswillbeginconducting,whichcouldresultinerraticoperation.Forthisreason,theseESDdiodesshouldNOTbeusedtoclamptheinputsignal. ThecapacitorC1inFigure51hasatypicalvalueof3pF,andismainlythepackagepincapacitance.ResistorR1istheonresistanceofthemultiplexerandtrack/holdswitch,andistypically500ohms.CapacitorC2istheADC104S051samplingcapacitor,andistypically30pF.TheADC104S051willdeliverbestperformancewhendrivenbyalow-impedancesourcetoeliminatedistortioncausedbythechargingofthesamplingcapacitance.ThisisespeciallyimportantwhenusingtheADC104S051tosampleACsignals.Alsoimportantwhensamplingdynamicsignalsisaband-passorlow-passfiltertoreduceharmonicsandnoise,improvingdynamicperformance. 18 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013 VA VINC13pF D1 C2 R130pF D2 ConversionPhase-SwitchOpenTrackPhase-SwitchClosed Figure51.EquivalentInputCircuit DIGITALINPUTSANDOUTPUTS TheADC104S051'sdigitaloutputDOUTislimitedby,andcannotexceed,thesupplyvoltage,VA.Thedigitalinputpinsarenotpronetolatch-upand,andalthoughnotmended,SCLK,CSandDINmaybeassertedbeforeVAwithoutanylatchuprisk. POWERSUPPLYCONSIDERATIONS TheADC104S051isfullypowered-upwheneverCSislow,andfullypowered-downwheneverCSishigh,withoneexception:theADC104S051automaticallyenterspower-downmodebetweenthe16thfallingedgeofaconversionandthe1stfallingedgeofthesubsequentconversion(seeTimingDiagrams). TheADC104S051canperformmultipleconversionsbacktoback;eachconversionrequires16SCLKcycles.TheADC104S051willperformconversionscontinuouslyaslongasCSisheldlow. Theusermaytradeoffthroughputforpowerconsumptionbysimplyperformingfewerconversionsperunittime.ThePowerConsumptionvs.SampleRatecurveintheTypicalPerformanceCharacteristicssectionshowsthetypicalpowerconsumptionoftheADC104S051versusthroughput.Tocalculatethepowerconsumption,simplymultiplythefractionoftimespentinthenormalmodebythenormalmodepowerconsumption,andaddthefractionoftimespentinshutdownmodemultipliedbytheshutdownmodepowerdissipation. PowerManagement WhentheADC104S051isoperatedcontinuouslyinnormalmode,themaximumthroughputisfSCLK/16.ThroughputmaybetradedforpowerconsumptionbyrunningfSCLKatitsmaximum8MHzandperformingfewerconversionsperunittime,puttingtheADC104S051intoshutdownmodebetweenconversions.AplotoftypicalpowerconsumptionversusthroughputisshownintheTypicalPerformanceCharacteristicssection.Tocalculatethepowerconsumptionforagiventhroughput,multiplythefractionoftimespentinthenormalmodebythenormalmodepowerconsumptionandaddthefractionoftimespentinshutdownmodemultipliedbytheshutdownmodepowerconsumption.Generally,theuserwillputthepartintonormalmodeandthenputthepartbackintoshutdownmode.Notethatthecurveofpowerconsumptionvs.throughputisnearlylinear.Thisisbecausethepowerconsumptionintheshutdownmodeissosmallthatitcanbeignoredforallpracticalpurposes. PowerSupplyNoiseConsiderations Thechargingofanyoutputloadcapacitancerequirescurrentfromthepowersupply,VA.Thecurrentpulsesrequiredfromthesupplytochargetheoutputcapacitancewillcausevoltagevariationsonthesupply.Ifthesevariationsarelargeenough,theycoulddegradeSNRandSINADperformanceoftheADC.Furthermore,dischargingtheoutputcapacitancewhenthedigitaloutputgoesfromalogichightoalogiclowwilldumpcurrentintothediesubstrate,whichisresistive.Loaddischargecurrentswillcause"groundbounce"noiseinthesubstratethatwilldegradenoiseperformanceifthatcurrentislargeenough.Thelargeristheoutputcapacitance,themorecurrentflowsthroughthediesubstrateandthegreateristhenoisecoupledintotheanalogchannel,degradingnoiseperformance. Tokeepnoiseoutofthepowersupply,keeptheoutputloadcapacitanceassmallaspractical.Iftheloadcapacitanceisgreaterthan50pF,usea100ΩseriesresistorattheADCoutput,locatedasclosetotheADCoutputpinaspractical.Thiswilllimitthechargeanddischargecurrentoftheoutputcapacitanceandimprovenoiseperformance. Copyright©2004–2013,TexasInstrumentsIncorporatedProductFolderLinks:ADC104S051 SubmitDocumentationFeedback 19 ADC104S051 SNAS253G–NOVEMBER2004–REVISEDMARCH2013REVISIONHISTORY ChangesfromRevisionF(March2013)toRevisionG Page •ChangedlayoutofNationalDataSheettoTIformat
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19 20 SubmitDocumentationFeedback ProductFolderLinks:ADC104S051Copyright©2004–2013,TexasInstrumentsIncorporated PACKAGEOPTIONADDENDUM 23-Aug-2017 PACKAGINGINFORMATION OrderableDeviceADC104S051CIMM/NOPB Status(1) ACTIVE PackageTypePackageDrawing VSSOP DGS PinsPackageQty 101000 EcoPlan
(2) Green(RoHS&noSb/Br) Lead/BallFinish
(6) CUSN MSLPeakTemp
(3) Level-1-260C-UNLIM OpTemp(°C)-40to85
(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicemendedfornewdesigns.LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.NRND:Notmendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotmendusingthispartinanewdesign.PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. DeviceMarking (4/5) X11C
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatpliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.TImayreferencethesetypesofproductsas"Pb-Free".RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutpliantwithEURoHSpursuanttoaspecificEURoHSexemption.Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.-TheMoistureSensitivityLevelratingordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.IfalineisindentedthenitisacontinuationofthepreviouslineandthebinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Lead/BallFinish-OrderableDevicesmayhavemultiplematerialfinishoptions.Finishoptionsareseparatedbyaverticalruledline.Lead/BallFinishvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth. ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisoningmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis. Samples Addendum-Page1 TAPEANDREELINFORMATION PACKAGEMATERIALSINFORMATION 24-Aug-2017 *AlldimensionsarenominalDevice PackagePackageTypeDrawing Pins ADC104S051CIMM/NOPBVSSOPDGS10 SPQ1000 ReelReelDiameterWidth (mm)W1(mm) 178.012.4 A0(mm) 5.3 B0(mm) 3.4 K0(mm) 1.4 P1(mm) 8.0
W Pin1 (mm)Quadrant 12.0 Q1 PackMaterials-Page1 PACKAGEMATERIALSINFORMATION 24-Aug-2017 *AlldimensionsarenominalDevice ADC104S051CIMM/NOPB PackageTypeVSSOP PackageDrawingPins DGS 10 SPQ1000 Length(mm)210.0 Width(mm)185.0 Height(mm)35.0 PackMaterials-Page2 IMPORTANTNOTICE TexasInstrumentsIncorporated(TI)reservestherighttomakecorrections,enhancements,improvementsandotherchangestoitssemiconductorproductsandservicesperJESD46,latestissue,andtodiscontinueanyproductorserviceperJESD48,latestissue.Buyersshouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentplete. TI’spublishedtermsofsaleforsemiconductorproducts()applytothesaleofpackagedintegratedcircuitproductsthatTIhasqualifiedandreleasedtomarket.AdditionaltermsmayapplytotheuseorsaleofothertypesofTIproductsandservices. ReproductionofsignificantportionsofTIinformationinTIdatasheetsispermissibleonlyifreproductioniswithoutalterationandispaniedbyallassociatedwarranties,conditions,limitations,andnotices.TIisnotresponsibleorliableforsuchreproduceddocumentation.Informationofthirdpartiesmaybesubjecttoadditionalrestrictions.ResaleofTIproductsorserviceswithstatementsdifferentfromorbeyondtheparametersstatedbyTIforthatproductorservicevoidsallexpressandanyimpliedwarrantiesfortheassociatedTIproductorserviceandisanunfairanddeceptivebusinesspractice.TIisnotresponsibleorliableforanysuchstatements. BuyersandotherswhoaredevelopingsystemsthatincorporateTIproducts(collectively,“Designers”)understandandagreethatDesignersremainresponsibleforusingtheirindependentanalysis,evaluationandjudgmentindesigningtheirapplicationsandthatDesignershavefullandexclusiveresponsibilitytoassurethesafetyofDesigners'applicationsplianceoftheirapplications(andofallTIproductsusedinorforDesigners’applications)withallapplicableregulations,lawsandotherapplicablerequirements.Designerrepresentsthat,withrespecttotheirapplications,Designerhasallthenecessaryexpertisetocreateandimplementsafeguardsthat(1)anticipatedangerousconsequencesoffailures,(2)monitorfailuresandtheirconsequences,and(3)lessenthelikelihoodoffailuresthatmightcauseharmandtakeappropriateactions.DesigneragreesthatpriortousingordistributinganyapplicationsthatincludeTIproducts,DesignerwillthoroughlytestsuchapplicationsandthefunctionalityofsuchTIproductsasusedinsuchapplications. TI’sprovisionoftechnical,applicationorotherdesignadvice,qualitycharacterization,reliabilitydataorotherservicesorinformation,including,butnotlimitedto,referencedesignsandmaterialsrelatingtoevaluationmodules,(collectively,“TIResources”)areintendedtoassistdesignerswhoaredevelopingapplicationsthatincorporateTIproducts;bydownloading,essingorusingTIResourcesinanyway,Designer(individuallyor,ifDesignerisactingonbehalfofpany,Designer’pany)agreestouseanyparticularTIResourcesolelyforthispurposeandsubjecttothetermsofthisNotice. TI’sprovisionofTIResourcesdoesnotexpandorotherwisealterTI’sapplicablepublishedwarrantiesorwarrantydisclaimersforTIproducts,andnoadditionalobligationsorliabilitiesarisefromTIprovidingsuchTIResources.TIreservestherighttomakecorrections,enhancements,improvementsandotherchangestoitsTIResources.TIhasnotconductedanytestingotherthanthatspecificallydescribedinthepublisheddocumentationforaparticularTIResource. Designerisauthorizedtouse,copyandmodifyanyindividualTIResourceonlyinconnectionwiththedevelopmentofapplicationsthatincludetheTIproduct(s)identifiedinsuchTIResource.NOOTHERLICENSE,EXPRESSORIMPLIED,BYESTOPPELOROTHERWISETOANYOTHERTIINTELLECTUALPROPERTYRIGHT,ANDNOLICENSETOANYTECHNOLOGYORINTELLECTUALPROPERTYRIGHTOFTIORANYTHIRDPARTYISGRANTEDHEREIN,includingbutnotlimitedtoanypatentright,copyright,maskworkright,orotherintellectualpropertyrightrelatingtobination,machine,orprocessinwhichTIproductsorservicesareused.Informationregardingorreferencingthird-partyproductsorservicesdoesnotconstitutealicensetousesuchproductsorservices,orawarrantyorendorsementthereof.UseofTIResourcesmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthethirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI. TIRESOURCESAREPROVIDED“ASIS”ANDWITHALLFAULTS.TIDISCLAIMSALLOTHERWARRANTIESORREPRESENTATIONS,EXPRESSORIMPLIED,REGARDINGRESOURCESORUSETHEREOF,INCLUDINGBUTNOTLIMITEDTOACCURACYORCOMPLETENESS,TITLE,ANYEPIDEMICFAILUREWARRANTYANDANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ANDNON-INFRINGEMENTOFANYTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.TISHALLNOTBELIABLEFORANDSHALLNOTDEFENDORINDEMNIFYDESIGNERAGAINSTANYCLAIM,INCLUDINGBUTNOTLIMITEDTOANYINFRINGEMENTCLAIMTHATRELATESTOORISBASEDONANYCOMBINATIONOFPRODUCTSEVENIFDESCRIBEDINTIRESOURCESOROTHERWISE.INNOEVENTSHALLTIBELIABLEFORANYACTUAL,DIRECT,SPECIAL,COLLATERAL,INDIRECT,PUNITIVE,INCIDENTAL,CONSEQUENTIALOREXEMPLARYDAMAGESINCONNECTIONWITHORARISINGOUTOFTIRESOURCESORUSETHEREOF,ANDREGARDLESSOFWHETHERTIHASBEENADVISEDOFTHEPOSSIBILITYOFSUCHDAMAGES. UnlessTIhasexplicitlydesignatedanindividualproductasmeetingtherequirementsofaparticularindustrystandard(e.g.,ISO/TS16949andISO26262),TIisnotresponsibleforanyfailuretomeetsuchindustrystandardrequirements. WhereTIspecificallypromotesproductsasfacilitatingfunctionalsafetyorpliantwithindustryfunctionalsafetystandards,suchproductsareintendedtohelpenablecustomerstodesignandcreatetheirownapplicationsthatmeetapplicablefunctionalsafetystandardsandrequirements.Usingproductsinanapplicationdoesnotbyitselfestablishanysafetyfeaturesintheapplication.Designersmustpliancewithsafety-relatedrequirementsandstandardsapplicabletotheirapplications.DesignermaynotuseanyTIproductsinlife-criticalmedicalequipmentunlessauthorizedofficersofthepartieshaveexecutedaspecialcontractspecificallygoverningsuchuse.Life-criticalmedicalequipmentismedicalequipmentwherefailureofsuchequipmentwouldcauseseriousbodilyinjuryordeath(e.g.,lifesupport,pacemakers,defibrillators,heartpumps,neurostimulators,andimplantables).Suchequipmentincludes,withoutlimitation,allmedicaldevicesidentifiedbytheU.S.FoodandDrugAdministrationasClassIIIdevicesandequivalentclassificationsoutsidetheU.S. TImayexpresslydesignatecertainproductspletingaparticularqualification(e.g.,Q100,MilitaryGrade,orEnhancedProduct).DesignersagreethatithasthenecessaryexpertisetoselecttheproductwiththeappropriatequalificationdesignationfortheirapplicationsandthatproperproductselectionisatDesigners’ownrisk.Designersaresolelyresponsiblepliancewithalllegalandregulatoryrequirementsinconnectionwithsuchselection. DesignerwillfullyindemnifyTIanditsrepresentativesagainstanydamages,costs,losses,and/orliabilitiesarisingoutofDesigner’spliancewiththetermsandprovisionsofthisNotice. MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265Copyright©2017,TexasInstrumentsIncorporated
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