TMS470MF03107
ZHCS061C–JANUARY2012
TMS470MF04207/TMS470MF0310716/32位精简指令集(RISC)闪存微控制器
查询样片:TMS470MF04207,TMS470MF03107
1特性
1 •带有安全特性的高性能汽车级微控制器–完全车用温度范围–闪存和SRAM上的错误校正码(ECC)–CPU和内存BIST（内置自检） •ARMCortex™-M332位RISCCPU–高效1.2DMIPS/MHz–优化的Thumb2指令集–内存保护单元(MPU)–带有第三方支持的开放式架构–内置调试模块 •操作特性–高达80Mhz系统时钟–单个3.3V电源 •集成内存–带有ECC的448KB总程序闪存–支持闪存EEPROM仿真–带有ECC的24K字节静态RAM(SRAM) •关键外设–高端定时器，多缓冲模数转换器(MibADC)，控制器局域网络(CAN)，多缓冲串行外设接口(MibSPI) •通用TMS470M/570平台架构–系列产品上的一致内存映射–实时中断定时器(RTI)–数字安全装置–矢量中断模块(VIM)–循环冗余校验器(CRC) •基于调频零引脚锁相环路(FMzPLL)的时钟模块–振荡器和PLL时钟模块 •高达49个外设IO引脚–4个专用GIO-带有外部中断 •两个外部时钟前置分频器(ECP)模块–可编程低频外部时钟(ECLK)–一个专用引脚和一个复用ECLK/HET引脚 •通信接口–两个CAN控制器•一个有32个邮箱，另外一个有16个邮箱•邮箱RAM上的奇偶校验–两个多缓冲串行外设接口(MibSPI)•总数为12的芯片选择•64个缓冲器，每个缓冲器上均有奇偶校验–两个通用异步收发器(UART)(SCI)接口•针对本地互连网络（LIN2.1主控模式）的硬件支持 •高端定时器(HET)–多达16个可编程I/O通道–带有奇偶校验的128字高端定时器RAM •16通道10位多缓冲ADC(MibADC)–带有奇偶校验的64字FIFO缓冲器–单一或者连续转换模式–1.55µs最小采样/转换时间–校准模式和自检特性 •片载基于扫描的仿真逻辑电路–IEEE标准1149.1(JTAG)测试-访问端口和边界扫描 •支持的数据包–100引脚塑料四方扁平封装（PZ后缀）–绿色环保/无铅 •可用的开发工具–开发板–CodeComposerStudio集成开发环境(IDE)–HET汇编程序和模拟器–nowFlash™闪存编程工具 •社区资源–TIE2E社区
1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters. 版权©2012,TexasInstrumentsIncorporatedEnglishDataSheet:SPNS159 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 1.1PZ封装视图 ADIN[7]76ADIN[8]77ADIN[9]78ADIN[10]79ADIN[11]80ADIN[12]81ADREFHI82ADREFLO83 VSSAD84VCCAD85ADIN[13]86ADIN[14]87ADIN[15]88PORRST89MIBSPI2ENA90 ENZ91VCC92VSS93VCCIOR94VCCP95ECLK96TEST97RST98FLTP199VSS100 75ADIN[6]74ADIN[5]73ADIN[4]72ADIN[3]71ADIN[2]70ADIN[1]69ADIN[0]68ADEVT67VCC66VSS65VCCIOR64HET[15]/ECLK263HET[14]62HET[13]61HET[12]60HET[11]59HET[10]58HET[9]57HET[8]56HET[7]55HET[6]54HET[5]53HET[4]52VCCIOR51VSS 50HET[3] 49HET[2] 48TRST 47TMS 46TDI 45TDO 44TCK 43 VCCIOR 42VSS 41VCC 40HET[1] 39HET[0] 38CAN2SRX 37CAN2STX 36MIBSPI1SOMI 35MIBSPI1SIMO 34MIBSPI1CLK 33MIBSPI1SCS[0] 32MIBSPI1SCS[1] 31MIBSPI1SCS[2] 30MIBSPI1SCS[3] 29MIBSPI1SCS[4] 28MIBSPI1SCS[5] 27MIBSPI1SCS[6] 26MIBSPI1SCS[7] MIBSPI2SCS[0]1MIBSPI2SCS[1]2MIBSPI2SCS[2]3MIBSPI2SCS[3]
4 GIOA[4]/INT[4]5GIOA[5]/INT[5]
6 CAN1STX7CAN1SRX8 VSS9OSCIN10OSCOUT11 VCC12VSS13VCCIOR14GIOA[6]/INT[6]15GIOA[7]/INT[7]16MIBSPI2CLK17MIBSPI2SIMO18MIBSPI2SOMI19VCCIOR20VSS21LIN1SCI1TX22LIN1SCI1RX23LIN2SCI2TX24LIN2SCI2RX25 图1-
1.TMS470MF04207和TMS470MF03107100引脚PZ封装（顶视图）
2 特性 版权©2012,TexasInstrumentsIncorporated TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 1.2说明 TMS470MF04207/03107器件隶属于德州仪器(TI)的TMS470M汽车级16/32位精简指令集计算机(RISC)微控制器系列。
TMS470M微控制器利用高效率的Cortex™–M316/32位RISC中央处理单元(CPU)提供了高性能，由此实现了很高的指令吞吐量并保持了更加出色的代码效率。
TMS470M器件运用了大端字节序格式，在该格式中，一个字的最高有效字节被存储于编号最小的字节中，而最低有效字节则存储在编号最大的字节中。
高端嵌入式控制应用要求其控制器提供更多的性能并保持低成本。
TMS470M微控制器架构提供了针对这些性能和成本需求的解决方案，并保持了低功耗。
TMS470MF04207/03107器件的组成如下：•16/32位RISCCPU内核•TMS470MF04207高达448K字节的程序闪存（具有SECDEDECC）•TTMS470MF03107高达320K字节的程序闪存（具有SECDEDECC）•具有SECDEDECC的64K字节闪存（用于获得额外的程序空间或进行EEPROM仿真）•高达24K字节的静态RAM(SRAM)（具有SECDEDECC）•实时中断定时器(RTI)•矢量中断模块(VIM)•硬件内置自测试(BIST)校验器，用于SRAM(MBIST)和CPU(LBIST)•64位循环冗余校验器(CRC)•基于调频零引脚锁相环(FMzPLL)的时钟模块（带前置分频器）•两个多缓冲串行外设接口(MibSPI)•两个具有本地互连网络接口(LIN)的UART(SCI)•两个CAN控制器(DCAN)•高端定时器(HET)•外部时钟前置分频器(ECP)模块•一个16通道10位多缓冲ADC(MibADC)•错误信令模块(ESM)•4个专用的通用I/O(GIO)引脚和45个附加外设I/O(100引脚封装) TMS470M内存包括通用SRAM，可支持字节模式、半字模式及字模式的单周期读/写存取。
可以利用ECC对TMS470M器件上的SRAM加以保护。
此项特性运用单错纠正和双错检测电路（SECDED电路）来检测并选择性地校正单位错误以及检测所有的双位错误和某些多位错误。
这是通过将一个用于内存空间的每个64位双字的8位ECC校验和/代码保存在一个单独的ECCRAM内存空间中实现的。
该器件上的闪存是一种非易失性、电可擦且可编程的存储器。
它是采用一个144位宽的数据字（128位，无ECC）和一个64位宽的闪存模块接口实现的。
该闪存在高达28MHz的系统时钟频率条件下运行。
可提供闪存数据线性预读取的流水线模式实现了一个高达80MHz的系统时钟。
TMS470M器件上的增强型实时中断(RTI)模块可选择由振荡器时钟进行驱动。
数字安全装置(DWD)是一个25位的可复位递减计数器，当安全装置计数器终止计数时，该计数器将提供系统复位。
TMS470M器件具有6个通信接口：两个LIN/SCI、两个DCAN和两个MibSPI。
LIN是本地互连网络标准，而且还支持一种SCI模式。
SCI可被用在一个用于CPU与其他采用标准不归零制(NRZ)格式外设之间的异步通信的全双工、串行I/O接口中。
DCAN采用一种串行、多主机通信协议，此协议可高效支持分布式实时控制及高达1兆位每秒(Mbps)的稳健通信速率。
DCAN非常适合于工作于嘈杂和严酷环境中的应用（例如：汽车和工业领域），此类应用需要可靠的串行通信或多路复用线路。
MibSPI为相似的移位寄存器型器件之间的高速通信提供了一种便捷的串行交互方法。
MibSPI提供了标准的SOMI、SIMO和SPI时钟接口以及多达8条芯片选择线路。
版权©2012,TexasInstrumentsIncorporated 特性
3 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 HET是一种先进的智能定时器，可为实时应用提供精密的定时功能。
该定时器为软件控制型，采用一个精简指令集，并具有一个专用的微级机定时器和一个连接的I/O端口。
这种HET可用于比较、捕获或通用型I/O。
它特别适合于那些需要带有复杂和准确的时间脉冲的多种传感器信息和驱动传动器的应用。
TMS470MHET外设包含“异或(XOR)共享”功能。
该功能允许对两个相邻的HET高分辨率通道进行“异或”运算，从而可以输出一个小于标准HET的脉冲。
TMS470M器件具有一个10位分辨率的采样及保持MibADC。
可利用软件对每个MibADC通道进行分组，以用于顺序转换序列。
有三个单独的分组，它们均可以由一个外部事件触发。
每个序列可在被触发时执行一次转换，或者通过配置以执行连续转换模式。
调频零引脚锁相环(FMzPLL)时钟模块包含一个锁相环、一个时钟监视器电路、一个时钟启用电路和一个前置分频器。
FMzPLL的功能是将外部频率基准倍频至一个较高的频率，以供内部使用。
FMzPLL提供了全局时钟模块(GCM)的输入。
GCM模块接着向所有其他的TMS470M器件模块提供系统时钟(HCLK)、实时中断时钟(RTICLK)、CPU时钟(GCLK)、HET时钟(VCLK2)、DCAN时钟(AVCLK1)及外设接口时钟(VCLK)。
另外，TMS470MF04207/TMS470MF03107器件还具有两个外部时钟前置分频器(ECP)模块，该模块在被启用时将输出一个连续外部时钟(ECLK)。
ECLK1频率是外设接口时钟(VCLK)频率的一个用户可编程比值。
可以选择第二个ECLK输出来取代HET15输出。
它与ECLK1共用同一个信源时钟，但可以针对一个产生自ECLK1的单独输出频率进行独立设置。
错误信令模块(ESM)在器件内部提供了一个用于错误报告的共用位置，从而实现了高效的错误检查和识别。
4 特性 版权©2012,TexasInstrumentsIncorporated 1.3功能方框图图1-2显示了TMS470M器件的功能方框图。
TMS470MF04207/TMS470MF03107 LBIST JTAG-DP nVIC Cortex™M3 withMPU IDSYS M3VIM VCCPFLTP1 BMM BMM Flash RAM PSA A2V Upto384KB Upto24KB w/ECC w/ECC Flash64KBw/ECC MBIST OSCIN1OSCOUT1 VCCIORENZ VCCVCCVCCVCC OSCPLLCLKMonitor 1.5-VP-ChVREG VCCOUT Passgate1 Passgate2 Passgate3 Passgate4 PCR FlashWrapper RAMWrapper RTI/DWD TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 ICEPICK BoundaryScan HET128Words w/ParityESM SYS LIN/SCI1 LIN/SCI2 MibSPI164Words/16TGsw/Parity MibSPI264Words/8TGsw/Parity TMSTCKTRSTTDITDO HET[15:0] RSTPORRSTTESTECLKLIN/SCI1TXLIN/SCI1RXLIN/SCI2TXLIN/SCI2RXMIBSPI1SIMOMIBSPI1SOMIMIBSPI1CLKMIBSPI1SCS[7:0]MIBSPI2SIMOMIBSPIP2SOMIMIBSPI2CLKMIBSPI2SCS[3:0]MIBSPI2ENA ADC64Wordsw/Parity DCAN116Mailboxes w/Parity DCAN232Mailboxes w/Parity GIO ADIN[15:0]ADEVTVCCADVSSADADREFHIADREFLOCANS1RXCANS1TX CANS2RXCANS2TX GIOOA[7:4]/INTA[7:4] 图1-
2.TMS470M系列方框图 版权©2012,TexasInstrumentsIncorporated 特性
5 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 1.4术语和首字母缩略词 术语和首字母缩略词A2V ADCAHBBMM CRCDAPDCANDWDECCESMGIOHETICEPICK JTAGJTAG-DP LBISTLIN M3VIMMBISTMibSPIMPUNVICOSCPCR PLLPSARTISCISECDEDSTCSYSVBUSVBUSPVREG 表1-
1.术语和首字母缩略词 描述AHB至VBUSP桥接 模数转换器高级高性能总线总线矩阵主控 循环冗余校验控制器调试访问端口控制器局域网数字安全装置错误校正码错误信令模块通用输入/输出高端定时器 处于电路仿真TAP（测试访问端口）选择模块 联合测试访问组JTAG调试端口 逻辑内置自检本地互连网络Cortex-M3矢量中断管理器存储器内置自检多缓冲串行外设接口 保护单元嵌套矢量中断控制器 振荡器外设中心资源 锁相环路并行签名分析 实时中断串行通信接口单一错误校正和双错误校正自检控制器 系统模块虚拟总线虚拟管道型总线电压稳压器 注释A2V桥接提供私有TIVBUSP和TMS470M平台器件中ARM AHB总线间的内存接口。
M3内核的部件 BMM提供不同总线受控模块到不同总线主控模块的连接性。
如果没有发生资源冲突或者如果主控模块在仲裁过程中保持并行的 话，来自不同总线模块的访问可并行执行。
DAP是一个ARM调试接口的工具。
ICEPick能够连接或者隔离一个模块级TAP到一个更高级芯片TAP的数据通信。
ICEPick设计时充分考虑了仿真和测试需 要。
负责测试访问端口的IEEE委员会JTAG-DP包含一个调试端口状态机(JTAG)，此状态机控制JTAG-DP运行，包括控制扫描链路接口，此接口提供到JTAGDP的外部物理接口。
它基于JTAGTAP状态机，请见IEEE 标准1149.1-2001。
测试M3CPU的完整性 测试SRAM的完整性 M3内核的部件 包括CBA（通用总线架构）的协议中的一个包括CBA（通用总线架构）的协议中的一个
6 特性 版权©2012,TexasInstrumentsIncorporated 1特性.........................................................11.1PZ封装视图.........................................21.2说明..................................................31.3功能方框图...........................................51.4术语和首字母缩略词.................................6 2DeviceOverview........................................82.1MemoryMapSummary..............................92.2TerminalFunctions.................................142.3DeviceSupport.....................................18 3DeviceConfigurations................................203.1Reset/AbortSources...............................203.2LockupResetModule..............................213.3ESMAssignments..................................213.4InterruptPriority(M3VIM)..........................223.5MibADC.............................................233.6MibSPI..............................................243.7JTAGID............................................253.8ScanChains........................................253.9AdaptiveImpedance4mAIOBuffer...............253.10Built-InSelfTest(BIST)Features..................293.11DeviceIdentificationCodeRegister................32 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 3.12DevicePartNumbers...............................334DeviceOperatingConditions.......................34 4.1AbsoluteMaximumRatingsOverOperatingFree- AirTemperatureRange,QVersion................344.2DevicemendedOperatingConditions......34 4.3ElectricalCharacteristicsOvermendedOperatingFree-AirTemperatureRange,QVersion ......................................................35 5PeripheralInformationandElectrical Specifications..........................................365.1RSTandPORRSTTimings........................365.2PLLandClockSpecifications......................395.3SPInMasterModeTimingParameters............505.4SPInSlaveModeTimingParameters..............545.5CANController(DCANn)ModeTimings...........585.6High-EndTimer(HET)Timings....................585.7Multi-BufferedA-to-DConverter(MibADC).........596RevisionHistory.......................................637MechanicalData.......................................647.1ThermalData.......................................647.2PackagingInformation..............................64 Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 内容
7 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 2DeviceOverview TheTMS470MF04207/03107deviceisaTMS470MPlatformArchitectureimplementedinF035130-nmTItechnology.Table2-1identifiesallthecharacteristicsoftheTMS470MF04207/03107deviceexcepttheSYSTEMandCPU,whicharegeneric. Table2-
1.DeviceCharacteristics CHARACTERISTICS DEVICEDESCRIPTIONTMS470MF04207/03107 COMMENTSFORTMS470M MEMORY INTERNALMEMORY Pipeline/Non-Pipeline2Bankswithupto448K-Byte FlashwithECCUpto24K-ByteSRAMwithECC CRC,1-channel Flashispipeline-capable PERIPHERALS Forthedevice-specificinterruptpriorityconfigurations,seeTable3-
4.Fortheperipheraladdressrangesandtheirperipheralselects,seeTable2-
7. CLOCK FMzPLL Frequency-modulatedzero-pinPLLhasnoexternalloopfilterpins. GENERAL-PURPOSEI/Os 4I/O TheGIOAporthasuptofour(4)externalpinswithexternalinterruptcapability. LIN/SCI 2LIN/SCI DCAN 2DCAN Eachwith16/32mailboxes,respectively. MibSPI 2MibSPI OneMibSPIwitheightchipselectpins,16transfergroups,anda64wordbufferwithparity.AsecondMibSPIwithfourchipselectpins,1enablepin,8transfergroups,anda64wordbufferwithparity. HETwithXORShare 16I/O Thehigh-resolution(HR)SHAREfeatureallowseven-numberedHRpinstosharethenexthigherodd-numberedHRpinstructures.ThisHRsharingisindependentofwhetherornottheoddpinisavailableexternally.Ifanoddpinisavailableexternallyandshared,thentheoddpincanonlybeusedasageneral-purposeI/O.HETRAMwithparitycheckingcapability. HETRAM 128-InstructionCapacity MibADC 10-bit,16-channel64-wordFIFO MibADCRAMincludesparitysupport. COREVOLTAGE 1.55V Thecorevoltageissuppliedandregulatedbythedevice'sinternalvoltageregulator.Thereisnotneedforanexternallysuppliedcorevoltage. I/OVOLTAGE 3.3V PINS 100 Availableina100-pinpackage. PACKAGE PZ(100pin) The100-pinpackagedesignatorisPZ.
8 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 2.1MemoryMapSummary2.1.1MemoryMap Figure2-1andFigure2-2showtheTMS470MF04207andTMS470MF03107memorymaps. 0xFFFFFFFF0xFFF800000xFFF7FFFF 0xFF0000000xFEFFFFFF0xFE000000 SYSTEMModulePeripheralsPSA 0x08405FFF0x08400000 RAM-ECC 0x08105FFF0x08100000 RAM-CLRSpace(A)(24KB) 0x08085FFF0x08080000 RAM-SETSpace(A)(24KB) 0x08005FFF0x08000000 0x0047FFFF0x004400000x0042FFFF0x004000000x0008FFFF 0x000800000x0005FFFF RAM(24KB)FLASH-ECC(Bank1)FLASH-ECC(Bank0)FLASH(64KB-Bank1) 0x00000000 FLASH(384KB-Bank0)
A.TheRAMsupportsbitessoperationwhichallowsset/cleartodedicatedbitswithoutdisturbingtheotherbits;fordetaileddescription,seetheArchitectureSpecification. Figure2-
1.TMS470MF04207MemoryMap Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview
9 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 0xFFFFFFFF0xFFF800000xFFF7FFFF 0xFF0000000xFEFFFFFF0xFE000000 SYSTEMModulePeripheralsPSA 0x08403FFF0x08400000 RAM-ECC 0x08103FFF0x08100000 RAM-CLRSpace(A)(16KB) 0x08083FFF0x08080000 RAM-SETSpace(A)(16KB) 0x08003FFF0x08000000 0x00447FFF0x004400000x0041FFFF0x00400000 0x0008FFFF0x000800000x0003FFFF RAM(16KB)FLASH-ECC(Bank1)FLASH-ECC(Bank0)FLASH(64KB-Bank1) FLASH(256KB-Bank0) 0x00000000A.TheRAMsupportsbitessoperationwhichallowsset/cleartodedicatedbitswithoutdisturbingtheotherbits;for detaileddescription,seetheArchitectureSpecification. Figure2-
2.TMS470MF03107MemoryMap 10 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 2.1.2MemorySelects MemoriesintheTMS470Mdevicesarelocatedatfixedaddresses.Table2-2throughTable2-7detailthemappingofthememoryregions. Table2-
2.TMS470MF04207-SpecificMemoryFrameAssignment MEMORYFRAMENAME STARTADDRESS ENDINGADDRESS MEMORYTYPE ACTUALMEMORY nCS0
(1) 0x000000000x00080000 0x0005FFFF0x0008FFFF FlashFlash 384KBytes64KBytes RAM-CLR 0x08100000 0x08105FFF InternalRAM 24KBytes RAM-SET 0x08080000 0x08085FFF InternalRAM 24KBytes CSRAM0
(1) 0x080000000x08400000 0x08005FFF0x08405FFF InternalRAMInternalRAM-ECC 24KBytes24KBytes
(1)Additionaladdressmirroringcouldbepresentresultingininvalidbutaddressablelocationsbeyondthoselistedabove.TImendstheuseoftheMPUforprotectingesstoaddressesoutsidetheintendedrangeofuse. Table2-
3.TMS470MF03107-SpecificMemoryFrameAssignment MEMORYFRAMENAME STARTADDRESS ENDINGADDRESS MEMORYTYPE ACTUALMEMORY nCS0
(1) 0x000000000x00080000 0x0003FFFF0x0008FFFF FlashFlash 256KBytes64KBytes RAM-CLR 0x08100000 0x08103FFF InternalRAM 16KBytes RAM-SET 0x08080000 0x08083FFF InternalRAM 16KBytes CSRAM0
(1) 0x080000000x08400000 0x08003FFF0x08403FFF InternalRAMInternalRAM-ECC 16KBytes16KBytes
(1)Additionaladdressmirroringcouldbepresentresultingininvalidbutaddressablelocationsbeyondthoselistedabove.TImendstheuseoftheMPUforprotectingesstoaddressesoutsidetheintendedrangeofuse. Table2-
4.MemoryInitializationandMBIST CONNECTINGMODULE ADDRESSRANGEBASEADDRESSENDINGADDRESS MEMORYINITIALIZATIONCHANNEL MBISTCONTROLLERENABLECHANNEL SystemRAM(TMS470MF04207) 0x08000000 0x08005FFF
0 0 SystemRAM(TMS470MF03107) 0x08000000 0x08003FFF
0 0 MibSPI1RAM 0xFF0E0000 0xFF0FFFFF
1 MibSPI2RAM 0xFF0C0000 0xFF0DFFFF
2 1or2
(1) DCAN1RAM 0xFF1E0000 0xFF1FFFFF
3 DCAN2RAM 0xFF1C0000 0xFF1DFFFF
4 3or4
(1) ADCRAM 0xFF3E0000 0xFF3FFFFF
5 5 HETRAM 0xFF460000 0xFF47FFFF NotAvailable
6 STCROM NotApplicable NotApplicable NotApplicable
7
(1)TherearesingleMBISTcontrollersforbothMibSPIRAMsandbothDCANRAMs.TheMBISTcontrollerforbothMibSPIRAMsismappedtochannels1and2andtheMBISTcontrollerforbothDCANRAMsismappedtochannels3and4.MBISTonthesemodulescanbeinitiatedbyselectingoneofthe2channelsorboth. Table2-
5.PeripheralMemoryChipSelectAssignment CONNECTINGMODULE MibSPI1RAMMibSPI2RAMDCAN1RAMDCAN2RAM ADDRESSRANGE BASEADDRESSENDINGADDRESS 0xFF0E0000 0xFF0FFFFF 0xFF0C0000 0xFF0DFFFF 0xFF1E0000 0xFF1FFFFF 0xFF1C0000 0xFF1DFFFF PERIPHERALSELECTS PCS[7]PCS[6]PCS[14]PCS[15] Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview 11 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table2-
5.PeripheralMemoryChipSelectAssignment(continued) CONNECTINGMODULE ADCRAMHETRAM ADDRESSRANGE BASEADDRESSENDINGADDRESS 0xFF3E0000 0xFF3FFFFF 0xFF460000 0xFF47FFFF PERIPHERALSELECTS PCS[31]PCS[35] NOTEAllusedperipheralmemorychipselectsshoulddecodedowntothesmallestpossibleaddressforthisparticularperipheralconfiguration,startingfrom4kBupwards.Unusedaddressesshouldgenerateanillegaladdresserrorwhenessed. Table2-
6.SystemPeripheralRegisters FRAMENAME PSAFlashWrapperRegisters PCRRegisterSystemFrame2Registers CPUSTC(LBIST)ESMRegister RAMECCRegisterRTIRegisterVIMRegister SystemRegisters ADDRESSRANGE FRAMESTARTADDRESSFRAMEENDINGADDRESS 0xFE000000 0xFEFFFFFF 0xFFF87000 0xFFF87FFF 0xFFFFE000 0xFFFFE0FF 0xFFFFE100 0xFFFFE1FF 0xFFFFE400 0xFFFFE4FF 0xFFFFF500 0xFFFFF5FF 0xFFFFF900 0xFFFFF9FF 0xFFFFFC00 0xFFFFFCFF 0xFFFFFE00 0xFFFFFEFF 0xFFFFFF00 0xFFFFFFFF Table2-
7.PeripheralSelectMapwithAddressRange CONNECTINGMODULE MibSPI2MibSPI1LIN/SCI1LIN/SCI2DCAN2DCAN1 ADCGIOHET BASEADDRESS 0xFFF7F6000xFFF7F4000xFFF7E5000xFFF7E4000xFFF7DE000xFFF7DC000xFFF7C0000xFFF7BC000xFFF7B800 ENDADDRESS 0xFFF7F7FF0xFFF7F5FF0xFFF7E5FF0xFFF7E4FF0xFFF7DFFF0xFFF7DDFF0xFFF7C1FF0xFFF7BCFF0xFFF7B8FF PERIPHERALSELECTSPS[2] PS[6] PS[8]PS[15]PS[16]PS[17] 2.1.3FlashMemory Wheninpipelinemode,theFlashoperateswithasystemclockfrequencyofupto80MHz(versusasystemclockinnon-pipelinemodeofupto28MHz).Flashinpipelinemodeiscapableofessing128bitwordsandprovidesfour32-bitpipelinedwordstotheCPU. 12 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 NOTE
1.Afterasystemreset,pipelinemodeisdisabled[FRDCNTL[2:0]is000b,seetheFlashchapterintheTMS470MSeriesTechnicalReferenceManual(literaturenumberSPNU495)].Inotherwords,thedevicepowersupesoutofresetinnonpipelinemode.
2.Theflashexternalpumpvoltage(VCCP)isrequiredforalloperations(program,erase,andread). 2.1.4FlashProgramandErase TheTMS470MF04207/TMS470MF03107devicesflashcontainone384/256K-bytememoryarray(orbank)andone64K-bytebankforatotalofupto12sectors.Table2-8andTable2-9showtheTMS470MF04207andTMS470MF03107flashmemorybanksandsectors. Theminimumsizeforaneraseoperationisonesector.Themaximumsizeforaprogramoperationisone32-bitword. Table2-
8.TMS470MF04207FlashMemoryBanksandSectors SECTORNO. SEGMENT LOWADDRESS HIGHADDRESS
0 16k 0x00000000 0x00003FFF
1 16k 0x00004000 0x00007FFF
2 32k 0x00008000 0x0000FFFF
3 64k 0x00010000 0x0001FFFF
4 64k 0x00020000 0x0002FFFF
5 64k 0x00030000 0x0003FFFF
6 64k 0x00040000 0x0004FFFF
7 64k 0x00050000 0x0005FFFF
0 16k 0x00080000 0x00083FFF
1 16k 0x00084000 0x00087FFF
2 16k 0x00088000 0x0008BFFF
3 16k 0x0008C000 0x0008FFFF
(1)Bank1canbeusedaseitherEEPROMemulationspaceorasprogramspace. MEMORYARRAYS(ORBANKS) BANK0(384KBytes) BANK1
(1)(64KBytes) Table2-
9.TMS470MF03107FlashMemoryBanksandSectors SECTORNO. SEGMENT LOWADDRESS HIGHADDRESS
0 16k 0x00000000 0x00003FFF
1 16k 0x00004000 0x00007FFF
2 32k 0x00008000 0x0000FFFF
3 64k 0x00010000 0x0001FFFF
4 64k 0x00020000 0x0002FFFF
5 64k 0x00030000 0x0003FFFF
0 16k 0x00080000 0x00083FFF
1 16k 0x00084000 0x00087FFF
2 16k 0x00088000 0x0008BFFF
3 16k 0x0008C000 0x0008FFFF
(1)Bank1canbeusedaseitherEEPROMemulationspaceorasprogramspace. MEMORYARRAYS(ORBANKS) BANK0(256KBytes) BANK1
(1)(64KBytes) Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview 13 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 2.2TerminalFunctions Theterminalfunctionstable(Table2-10)identifiesthepinnames,theassociatedpinnumbers,inputvoltage,outputvoltage,whetherthepinhasanyinternalpullup/pulldownresistorsandafunctionalpindescription.TheTMS470MF04207andTMS470MF03107deviceshavethesamepinout. TERMINAL NAME 100PIN HET[0] 39 HET[1] 40 HET[2] 49 HET[3] 50 HET[4] 53 HET[5] 54 HET[6] 55 HET[7] 56 HET[8] 57 HET[9] 58 HET[10] 59 HET[11] 60 HET[12] 61 HET[13] 62 HET[14] 63 HET[15]/ECLK2 64 CAN1STX
7 CAN1SRX
8 CAN2STX 37 CAN2SRX 38 GIOA[4]/INT[4]
5 GIOA[5]/INT[5]
6 GIOA[6]/INT[6] 15 GIOA[7]/INT[7] 16 Table
2-10.TerminalFunctions INPUTVOLTAGE
(1)
(2) OUTPUTCURRENT
(3) IPU/IPD
(4) HIGH-ENDTIMER(HET) DESCRIPTION 3.3-VI/O Adaptiveimpedance4 mA ProgrammableIPD(100µA) Timerinputcaptureorpare.TheHET[15:0]applicablepinscanbeprogrammedasgeneral-purposeinput/output(GIO)pins. Thehigh-resolution(HR)SHAREfeatureallowsevenHRpinstosharethenexthigheroddHRpinstructure.ThenexthigheroddHRpinstructureisalwaysimplemented,evenifthenexthigheroddHRpadand/orpinitselfisnot. Note:HET[15]ismuxedwithECLK2output.IfECLK2outputisenabled(throughSYSPC1registerat0xFFFFFF00),ECLK2isoutputonthispinandHET[15]esaninternalonlyHETchannel. Note:ECLK2sourceselectmustbeprogrammedthesameasECLK1duetodevicespecificimplementationdetails. Note:ECLK2isenabledandECLK2dividerisprogrammedthroughECPcontrolregister1inSystemFrame2Registers(0xFFFFE128). 3.3-VI/O3.3-VI/O3.3-VI/O CANCONTROLLER1(DCAN1) Adaptiveimpedance4 mA ProgrammableIPU(100µA) DCAN1transmitpinorGIOpin.DCAN1receivepinorGIOpin. CANCONTROLLER2(DCAN2) Adaptiveimpedance4 mA ProgrammableIPU(100µA) DCAN2transmitpinorGIOpinDCAN2receivepinorGIOpin GENERAL-PURPOSEI/O(GIO) Adaptiveimpedance4 mA ProgrammableIPD(100µA) General-purposeinput/outputpins.Theyareinterrupt-capablepins.
(1)PWR=power,GND=ground,REF=referencevoltage,NC=noconnect
(2)AllI/Opins,exceptRST,areconfiguredasinputswhilePORRSTislowandimmediatelyafterPORRSTgoeshigh.
(3)TheTMS470Mdeviceutilizesadaptiveimpedance4mAbuffersthatdefaulttoanadaptiveimpedancemodeofoperation.Asafail-safe, theadaptiveimpedancefeaturesofthebuffermaybedisabledandrevertthebuffertoastandardbuffermode.
(4)IPD=internalpulldown,IPU=internalpullup(allinternalpullupsandpulldownsareinactiveoninputpinswhenPORRSTisasserted) 14 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table2-10.TerminalFunctions(continued) TERMINAL NAME 100PIN INPUTVOLTAGE
(1)
(2) OUTPUTCURRENT
(3) IPU/IPD
(4) DESCRIPTION MIBSPI1CLKMIBSPI1SCS[0]MIBSPI1SCS[1]MIBSPI1SCS[2]MIBSPI1SCS[3]MIBSPI1SCS[4]MIBSPI1SCS[5]MIBSPI1SCS[6]MIBSPI1SCS[7]MIBSPI1SIMOMIBSPI1SOMI MibSPI2CLKMibSPI2SCS[0]MibSPI2SCS[1]MibSPI2SCS[2]MibSPI2SCS[3]MibSPI2ENAMibSPI2SIMO[0] MibSPI2SOMI[0] LIN/SCI1RXLIN/SCI1TXLIN/SCI2RXLIN/SCI2TX ADEVT MULTI-BUFFEREDSERIALPERIPHERALINTERFACE1(MIBSPI1) 34 MIBSPI1clock.MIBSPI1CLKcanbeprogrammed asaGIOpin. 33 32 31 30 MIBSPI1slavechipselect.MIBSPI1SCS[7:0]can 29 Adaptive ProgrammablebeprogrammedasaGIOpins. 283.3-VI/OimpemdaAnce4IPU(100µA) 27 26 35 MIBSPI1datastream.Slavein/masterout. MIBSPI1SIMOcanbeprogrammedasaGIOpin. 36 MIBSPI1datastream.Slaveout/masterin. MIBSPI1SOMIcanbeprogrammedasaGIOpin. MULTI-BUFFEREDSERIALPERIPHERALINTERFACE2(MibSPI2) 17 MibSPI2clock.MibSPI2CLKcanbeprogrammed asaGIOpin.
1 2 MibSPI2slavechipselectMibSPI2SCS[3:0]canbe
3 programmedasGIOpins.
4 Adaptive 90 3.3-VI/O impedance4 ProgrammableIPU(100µA) MibSPI2enablepin.MibSPI2ENAcanbe mA programmedasaGIOpin. 18 MibSPI2datastream.Slavein/masterout. MibSPI2SIMOpinscanbeprogrammedasaGIO pins. 19 MibSPI2datastream.Slaveout/masterin. MibSPI2SOMIpinscanbeprogrammedasGIO pins. LOCALINTERCONNECTNETWORK/SERIALCOMMUNICATIONSINTERFACE(LIN/SCI) 23 LIN/SCI1datareceive.Canbeprogrammedasa Adaptive ProgrammableGIOpin. 22 3.3-VI/O impedance4mA IPU(100µA)LIN/SCI1datatransmit.Canbeprogrammedasa GIOpin. 25 LIN/SCI2datareceive.Canbeprogrammedasa Adaptive ProgrammableGIOpin. 24 3.3-VI/O impedance4mA IPU(100µA)LIN/SCI2datatransmit.Canbeprogrammedasa GIOpin. MULTI-BUFFEREDANALOG-TO-DIGITALCONVERTER(MIBADC) 68 3.3-VI/O Adaptive ProgrammableMibADCeventinput.CanbeprogrammedasaGIO impedance4IPD(100µA)pin. mA Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview 15 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 TERMINAL NAME 100PIN ADIN[0] 69 ADIN[1] 70 ADIN[2] 71 ADIN[3] 72 ADIN[4] 73 ADIN[5] 74 ADIN[6] 75 ADIN[7] 76 ADIN[8] 77 ADIN[9] 78 ADIN[10] 79 ADIN[11] 80 ADIN[12] 81 ADIN[13] 86 ADIN[14] 87 ADIN[15] 88 ADREFHI 82 ADREFLO 83 VCCAD 85 VSSAD 84 OSCIN 10 OSCOUT 11 PORRST 89 RST 98 ECLK 96 TCK 44 TDI 46 TDO 45 TMS 47 TRST 48 Table
2-10.TerminalFunctions(continued) INPUTVOLTAGE
(1)
(2) OUTPUTCURRENT
(3) IPU/IPD
(4) DESCRIPTION 3.3V MibADCanaloginputpins. 3.3-VREFGNDREF3.3-VPWR GND1.55-VI1.55-VO3.3-VI 3.3-VI/O 3.3-VI/O 3.3-VI 3.3-VI/O 3.3-VI OSCILLATOR(OSC) SYSTEMMODULE(SYS)IPD(100µA) Adaptiveimpedance4 mA IPU(100µA) Adaptiveimpedance4 mA ProgrammableIPD(100µA) TEST/DEBUG(T/D) IPD(100µA) IPU(100µA) Adaptiveimpedance4 mA IPD(100µA) IPU(100µA)IPD(100µA) MibADCmodulehigh-voltagereferenceinput.MibADCmodulelow-voltagereferenceinput.MibADCanalogsupplyvoltage.MibADCanaloggroundreference. Crystalconnectionpinorexternalclockinput.Externalcrystalconnectionpin. Inputmasterchippower-upreset.ExternalVCCmonitorcircuitrymustassertapower-onreset.Bidirectionalreset.Theinternalcircuitrycanassertareset,andanexternalsystemresetcanassertadevicereset.Onthispin,theoutputbufferisimplementedasanopendrain(driveslowonly).Toensureanexternalresetisnotarbitrarilygenerated,TImendsthatanexternalpullupresistorbeconnectedtothispin.Bidirectionalpin.ECLKcanbeprogrammedasaGIOpin. Testclock.TCKcontrolsthetesthardware(JTAG).Testdatainpin.TDIinputsserialdatatothetestinstructionregister,testdataregister,andprogrammabletestaddress(JTAG).Testdataoutpin.TDOoutputsserialdatafromthetestinstructionregister,testdataregister,identificationregister,andprogrammabletestaddress(JTAG).SerialinputpinforcontrollingthestateoftheCPUtestessport(TAP)controller(JTAG).TesthardwareresettoTAP.IEEEStandard1149-1(JTAG)Boundary-ScanLogic. 16 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TERMINAL NAME 100PIN TEST 97 ENZ 91 FLTP1 99 VCCP1 95 VCCP2 95 VCC 12 41 67 92 VCCIOR 14 20 43 52 65 94 VSS
9 13 21 42 51 66 93 100 TMS470MF04207
TMS470MF03107 ZHCS061C–JANUARY2012 Table2-10.TerminalFunctions(continued) INPUTVOLTAGE
(1)
(2) OUTPUTCURRENT
(3) IPU/IPD
(4) DESCRIPTION 3.3-VI IPD(100µA) Testenable.Reservedforinternaluseonly.TImendsthatthispinbeconnectedtogroundorpulleddowntogroundbyanexternalresistor. Enables/disablestheinternalvoltageregulator. 0V-Enablesinternalvoltageregulator. 3.3-VI IPD(100µA)3.3V-Disablesinternalvoltageregulator. 3.3-VPWR1.55-VPWR Note:TheENZpinisprovidedtofacilitatetestingacrossthecorevoltagerangeandisnotintendedfordisablingtheonchipvoltageregulatorduringapplicationuse. FLASH FlashTestPad1pin.Forproperoperation,thispinmustconnectonlytoatestpadornotbeconnectedatall[noconnect(NC)].ThetestpadmustnotbeexposedinthefinalproductwhereitmightbesubjectedtoanESDevent. Flashexternalpumpvoltage(3.3V).ThispinisrequiredforbothFlashreadandFlashprogramanderaseoperations.VCCP1andVCCP2aredoublebondedtothesamepin. SUPPLYVOLTAGECORE(1.55V) VregoutputvoltagewhenVregisenabled.VCCinputwhenVregisdisabled. SUPPLYVOLTAGEDIGITALI/OANDREGULATOR(3.3V) 3.3-VPWR DigitalI/Oandinternalregulatorsupplyvoltage. SUPPLYGROUND GND DigitalI/Oandcoresupplygroundreference. Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview 17 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 2.3DeviceSupport 2.3.1DeviceandDevelopment-SupportToolNomenclature Todesignatethestagesintheproductdevelopmentcycle,TIassignsprefixestothepartnumbersofalldevicesandsupporttools.mercialfamilymemberhasoneofthreeprefixes:TMX,TMP,orTMS(e.g.,TMS470MF04207).TexasInstrumentsmendstwoofthreepossibleprefixdesignatorsforitssupporttools:TMDXandTMDS.Theseprefixesrepresentevolutionarystagesofproductdevelopmentfromengineeringprototypes(TMX/TMDX)throughfullyqualifiedproductiondevices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimentaldevicethatisnotnecessarilyrepresentativeofthefinaldevice'selectricalspecifications. TMP Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthaspletedqualityandreliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproductthathasnotpletedTexasInstrumentsinternalqualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMXandTMPdevicesandTMDXdevelopment-supporttoolsareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMSdevicesandTMDSdevelopment-supporttoolshavebeencharacterizedfully,andthequalityandreliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies. Predictionsshowthatprototypedevices(TMXorTMP)haveagreaterfailureratethanthestandardproductiondevices.TexasInstrumentsmendsthatthesedevicesnotbeusedinanyproductionsystembecausetheirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesaretobeused. TIdevicenomenclaturealsoincludesasuffixwiththedevicefamilyname.Thissuffixindicatesthepackagetype(forexample,PZ),thetemperaturerange(forexample,"Blank"ismercialtemperaturerange),andthedevicespeedrangeinmegahertz. Figure2-3illustratesthenumberingandsymbolnomenclaturefortheTMS470Mfamily. 18 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 FullPartNumber TMS470MF04
2 07B SPZQQ1R OrderablePartNumberS
4 MF04
2 07
B SPZQQ1R Prefix:TMS=TMSQualifiedP=TMPPrototypeX=TMXSamples CoreTechnology:4=470CortexM3 Architecture:MF=M3Flash FlashMemorySize:04=448KBytes03=320KBytes RAMMemorySize:2=24KBytes1=16KBytes PeripheralConfiguration: DieRevision:Blank=InitialDieA=FirstDieRevisionB=SecondDieRevision Technology/CoreVoltage:S=F035(130nm),1.5-VNominalCoreVoltage PackageType:PZ=100-PinQFPPackage(Green) TemperatureRange:Q=-40°Cto+125°
C QualityDesignator:Q1=Automotive ShippingOptions:R=TapeandReel NOTE:Thepartnumbergivenaboveisforillustrativepurposesonlyanddoesnotnecessarilyrepresentthespecificpartnumberorsiliconrevisiontowhichthisdocumentapplies. Figure2-
3.TMS470MDeviceNumberingConventions Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview 19 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 3DeviceConfigurations 3.1Reset/AbortSourcesResets/abortsarehandledasshowninTable3-
1.Table3-
1.Reset/AbortSources ERRORSOURCE 1)CPUTRANSACTIONSPrecisewriteerror(NCNB/StronglyOrdered)Precisereaderror(NCB/DeviceorNormal)Imprecisewriteerror(NCB/DeviceorNormal)Externalimpreciseerror(Illegaltransactionwithokresponse)Illegalinstruction SYSTEMMODE User/PrivilegeUser/PrivilegeUser/PrivilegeUser/Privilege User/Privilege M3LockupMPUessviolation User/PrivilegeUser/Privilege 2)SRAMECCsingleerror(correctable)ECCdoubleerror(uncorrectable) User/PrivilegeUser/Privilege 3)FLASHWITHECCECCsingleerror(correctable)ECCdoubleerror(uncorrectable) User/PrivilegeUser/Privilege 8)HETHETMemoryparityerror User/Privilege 9)MIBSPIMibSPI1memoryparityerrorMibSPI2memoryparityerror User/PrivilegeUser/Privilege 10)MIBADCMemoryparityerror User/Privilege 11)DCAN/CANDCAN1memoryparityerrorDCAN2memoryparityerror User/PrivilegeUser/Privilege 13)PLLPLLsliperror User/Privilege 14)CLOCKMONITORClockmonitorinterrupt User/Privilege 19)VOLTAGEREGULATOR outofrange n/a 20)CPUSELFTEST(LBIST)CPUSelftest(LogicBIST)error User/Privilege 21)ERRORSREFLECTEDINTHESYSESRREGISTER Power-UpReset/Vregoutofvoltage
(2) n/a ERRORRESPONSE PreciseAbort(CPU)PreciseAbort(CPU)ImpreciseAbort(CPU) ESMUndefinedInstructionTrap (CPU)
(1)ESM=>NMIAbort(CPU) ESMESM=>NMI ESMESM=>NMI ESM ESMESM ESM ESMESM ESM ESM Reset ESM Reset ESMHOOKUP,GROUP.CHANNEL n/an/an/a2.17n/a2.16n/a 1.262.6 1.62.4 1.7 1.171.18 1.19 1.211.23 1.10 1.11 n/a 1.27 n/a
(1)TheundefinedinstructiontrapisNOTdetectedoutsideoftheCPU.ThetrapistakenonlyifthecodereachestheexecutestageoftheCPU.
(2)Bothapower-onresetandVregout-of-rangeresetareindicatedbythePORSTbitintheSYSESRregister. 20 DeviceConfigurations Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table3-
1.Reset/AbortSources(continued) ERRORSOURCE SYSTEMMODE ERRORRESPONSE Oscillatorfail/PLLslip
(3)M3Lockup/LRMWatchdogtimelimitexceededCPUResetSoftwareResetExternalReset n/a Reset n/a Reset n/a Reset n/a Reset n/a Reset n/a Reset
(3)Oscillatorfail/PLLslipcanbeconfiguredinthesystemregister(SYS.PLLCTL1)togenerateareset. ESMHOOKUP,GROUP.CHANNEL n/an/an/an/an/an/a 3.2LockupResetModule Thelockupresetmodule(LRM)isimplementedmunicatealockupconditionbythecore.TheLRMprovidesasmallwatchdogtimerwhichcangenerateasystemresetincasealockupconditionthatisidentifiedbythecorecannotbeclearedbysoftware. 3.3ESMAssignments TheESMmoduleisintendedformunicationcriticalsystemfailuresinacentrallocation.Theerrorindicationisbyanerrorinterruptwhenthefailureisrecognizedfromanydetectionunit.TheESMmoduleconsistofthreeerrorgroupswith32inputseach.ThegenerationoftheinterruptsisshowninTable3-
2.ESMassignmentsarelistedinTable3-
3. Table3-
2.ESMGroups ERRORGROUPGroup1Group2Group3 INTERRUPT,LEVELmaskable,low/highnon-maskable,high NotUsed Table3-
3.ESMAssignments ERRORSOURCESGROUP1 ReservedFlash-ECCSingleBitHETmemoryparityerror ReservedPLLSlipErrorClockMonitorinterrupt ReservedMibSPI1memoryparityerrorMibSPI2memoryparityerrorMibADCmemoryparityerror ReservedDCAN1memoryparityerror ReservedDCAN2memoryparityerror ReservedSRAM-singlebitCPULBIST-selftesterror CHANNEL 0-5678-91011 12-1617181920212223 24-252627 Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceConfigurations 21 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table3-
3.ESMAssignments(continued) ERRORSOURCESReservedGROUP2Reserved Flash-Double-BitError(uncorrectable)Reserved SRAM-Double-BitError(uncorrectable)ReservedM3Lockup M3ExternalImpreciseAbortReserved CHANNEL28-31 0-34567-15161718-31 3.4InterruptPriority(M3VIM) TheTMS470Mplatforminterruptarchitectureincludesavectoredinterruptmanager(M3VIM)thatprovideshardwareassistanceforprioritizingandcontrollingthemanyinterruptsourcespresentonadevice.Tablemunicatesthedefaultinterruptrequestassignments. MODULES ESMReserved ESMSYSTEM RTIRTIRTIRTIRTIRTIReservedGIOGIOHETHETMibSPI1MibSPI1ReservedLIN/SCI2LIN/SCI2LIN/SCI1LIN/SCI1DCAN1DCAN1ADCADCADC Table3-
4.InterruptRequestAssignments INTERRUPTSOURCES ESMHighlevelinterrupt(NMI)(NMI) ESMLowlevelinterruptSoftwareinterrupt(SSI)pareinterrupt0pareinterrupt1pareinterrupt2pareinterrupt3RTIoverflowinterrupt0RTIoverflowinterrupt1 ReservedGIOInterruptAGIOInterruptBHETlevel0interruptHETlevel1interruptMibSPI1level0interruptMibSPI1level1interrupt ReservedLIN/SCI2level0interruptLIN/SCI2level1InterruptLIN/SCI1level0interruptLIN/SCI1level1InterruptDCAN1level0InterruptDCAN1level1InterruptADCeventgroupinterruptADCswgroup1interruptADCswgroup2interrupt DEFAULTVIMINTERRUPTREQUEST 01234567891011121314151617181920212223242526 22 DeviceConfigurations Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table3-
4.InterruptRequestAssignments(continued) MODULES MibSPI2MibSPI2DCAN2DCAN2 ADCReservedReservedDCAN1DCAN2Reserved INTERRUPTSOURCES MibSPI2level0interruptMibSPI2level1interruptDCAN2level0interruptDCAN2level1interruptADCmagnitudethresholdinterrupt ReservedReservedDCAN1IF3interruptDCAN2IF3interruptReserved DEFAULTVIMINTERRUPTREQUEST 27282930313233343536-47 3.5MibADC Themulti-bufferedanalog-to-digitalconverter(MibADC)eptsananalogsignalandconvertsthesignaltoa10-bitdigitalvalue. TheTMS470MMibADCmodulestoresitsdigitalresultsinoneofthreeFIFObuffers.ThereisoneFIFObufferforeachconversiongroup[event,group1(G1),andgroup2(G2)],andthetotalMibADCFIFOonthedeviceisdividedamongstthesethreeregions.Thesizeoftheindividualgroupbuffersaresoftwareprogrammable.MibADCbufferscanbeservicedbyinterrupts. Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceConfigurations 23 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 3.5.1MibADCEventTriggers Allthreeconversiongroupscanbeconfiguredforevent-triggeredoperation,providinguptothreeeventtriggeredgroups. Thetriggersourceandpolaritycanbeselectedindividuallyforgroup1,group2andtheeventgroupfromtheoptionsidentifiedinTable3-
5. Table3-
5.MibADCEventHookupConfiguration EVENTNO. SOURCESELECTBITSforG1orEVENT(G1SRC[2:0]orEVSRC[2:0]) SIGNALPINNAME
1 000 ADEVT
2 001 HET[1]
3 010 HET[3]
4 011 HET[16]
(1)
5 100 HET[18]
(1)
6 101 HET[24]
(1)
7 110 HET[26]
(1)
8 111 HET[28]
(1)
(1)Thesechannelsareavailableasinternalsignalseveniftheyarenotincludedaspins(节1.1). 3.6MibSPI Themulti-bufferedserialperipheralinterfacemoduleallowsCPUindependentmunicationswithsystemperipherals. TheMibSPI1modulecansupportupto16transfergroupsand8chipselects.Inaddition,upto4dataformatscanbesupportedallowingassignmentofvariousformatstoeachtransfergroup. TheMibSPI2modulecansupportupto8transfergroups,4chipselects,andupto4dataformats. 3.6.1MibSPIEventTrigger TheMibSPImodulehastheabilitytoautomaticallytriggerSPIeventsbasedoninternalandexternaleventtriggers. ThetriggersourcescanbeselectedindividuallyforeachtransfergroupfromtheoptionsidentifiedinTable3-
6. Table3-
6.MibSPI1andMibSPI2EventHookupConfiguration EVENTNO. DisabledEVENT0EVENT1EVENT2EVENT3EVENT4EVENT5EVENT6EVENT7EVENT8 SOURCESELECTBITSFORMIBSPIEVENTS TGXCTRLTRIGSRC[3:0]0000000100100011010001010110011110001001 SIGNALPINNAME NotriggersourceGIOA[0]
(1)GIOA[1]
(1)GIOA[2]
(1)GIOA[3]
(1)GIOA[4]GIOA[5]HET[20]
(1)HET[21]
(1)HET[22]
(1)
(1)Thesechannelsareavailableasinternalsignalseveniftheyarenotincludedaspins(节1.1). 24 DeviceConfigurations Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table3-
6.MibSPI1andMibSPI2EventHookupConfiguration(continued) EVENTNO. EVENT9EVENT10EVENT11EVENT12EVENT13EVENT14 SOURCESELECTBITSFORMIBSPIEVENTS TGXCTRLTRIGSRC[3:0]101010111100110111101111 SIGNALPINNAME HET[23]
(1)HET[28]
(1)HET[29]
(1)HET[30]
(1)HET[31]
(1)InternalTickCounter 3.7JTAGIDThe32-bitJTAGIDcodeforthisdeviceis0x0B8D802F. 3.8ScanChainsThedevicecontainsanICEPICKmoduletoessthedebugscanchains;seeFigure3-
1.Debugscanchain#0handlestheesstotheCPU.TheICEPICKscanIDis0x00366D05,whichisthesameasthedeviceID. TDITDO DAP CPU BoundaryScanChain#
0 ICEPICK BoundaryScan BoundaryScanInterface Figure3-
1.DebugScanChains 3.9AdaptiveImpedance4mAIOBufferTheadaptiveimpedance4mAbufferisabufferthathasbeenexplicitlydesignedtoaddresstheissueofdecouplingEMIsourcesfromthepinswhichtheydrive.Thisisplishedbyadaptivelycontrollingtheimpedanceoftheoutputbufferandshouldbeparticularlyeffectivewithcapacitiveloads.Theadaptiveimpedance4mAbufferfeaturestwomodesofoperation:ImpedanceControlMode,andLow-PowerMode/StandardBufferModeasdefinedbelow:•ImpedanceControlModeisenabledinthedesignbydefault.Thismodeadaptivelycontrolstheimpedanceoftheoutputbuffer. Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceConfigurations 25 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 •StandardBufferModeisusedtoconfigurethebufferbackintoagenericconfiguration.Thisbuffermodeisusedwhenitisnecessarytodrivetheoutputatveryhighspeeds,orwhenEMIreductionisnotaconcern. Table3-
7.AdaptiveImpedance4mABufferModeAvailability MODULEORPINNAMESYS.ECLKSYS.nRST SYS.TDI/TDOSYS.TMSCHETSCI1LIN/SCI2MIBSPI1MibSPI2Reserved MIBADC.ADEVTDCAN1DCAN2GIOA STANDARDBUFFERENABLE(SBEN)
(1)GPREG1.0GPREG1.1 StandardBufferEnabledStandardBufferEnabled GPREG1.2GPREG1.3GPREG1.4GPREG1.5GPREG1.6GPREG1.7GPREG1.8GPREG1.9GPREG1.10GPREG1.11
(1)SBENconfigurationcanbeachievedusingtheGPREGregisterwithinthesystemframe(0xFFFFFFA0). 26 DeviceConfigurations Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 3.9.1StandardBufferEnableRegister(GPREG1) Ageneralpurposeregisterwiththesystemframehasbeenutilizedtocontroltheenablingofstandardbuffermode.ThisregisterisshowninFigure3-2anddescribedinTable3-
8 NOTEIngeneral,alldeviceregistersaredefinedwithintheTRM(SPNU450);however,incaseswheretheregisterdefinitionisdevicespecific,theregisterisdefinedwithinthedevicespecificdatasheet. 31ReservedR-
0 15 12 11 10
9 Reserved GIOA_SBENDCAN2_SBENDCAN1_SBEN R-
0 RW-
0 RW-
0 RW-
0 7
6 5
4 Reserved MibSPI2_SBEN MIBSPI1_SBEN LIN2SCI2_SBEN RW-
0 RW-
0 RW-
0 RW-
0 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
3 LIN1SCI1_SBEN RW-
0 2HET_SBEN RW-
0 1RST_SBEN RW-
0 Figure3-
2.General-PurposeRegister1(GPREG1) 16 8ADC.ADEVT_ SBENRW-0 0ECLK_SBEN RW-
0 Bit31-12 11 10 9 8 76
5 Table3-
8.General-PurposeRegister1(GPREG1)FieldDescriptions FieldReservedGIOA_SBEN DCAN2_SBEN DCAN1_SBEN ADC.ADEVT_SBEN ReservedMibSPI2_SBEN MIBSPI1 Value 01 01 01 01 01 01 DescriptionThesebitsarereserved.Readsreturn0andwriteshavenoeffect.GIOAportstandardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallGIOApinsStandardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.DCAN2standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallDCAN2pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.DCAN1standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallDCAN1pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.ADC.ADEVTstandardbufferenablebit.Thisbitenables/disablesstandardbuffermodefortheADC.ADEVTpin.Standardbuffermodeisnotenabled.StandardbuffermodeisenabledfortheADEVTpin.Thesebitsarereserved.Readsreturn0andwriteshavenoeffect.MibSPI2standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallMibSPI2pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.MIBSPI1standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallMIBSPI1pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins. Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceConfigurations 27 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table3-
8.General-PurposeRegister1(GPREG1)FieldDescriptions(continued) BitField4LIN2SCI2_SBEN3LIN1SCI1_SBEN2HET_SBEN1RST_SBEN0ECLK_SBEN Value 01 01 01 01 01 DescriptionLIN/SCI2standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallLIN/SCI2pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.LIN/SCI1standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallLIN/SCI1pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.HETstandardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallHETpins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.RSTstandardbufferenablebit.Thisbitenables/disablesstandardbuffermodefortheRSTpin.Standardbuffermodeisnotenabled.StandardbuffermodeisenabledfortheRSTpin.ECLKstandardbufferenablebit.Thisbitenables/disablesstanda
1 •带有安全特性的高性能汽车级微控制器–完全车用温度范围–闪存和SRAM上的错误校正码(ECC)–CPU和内存BIST（内置自检） •ARMCortex™-M332位RISCCPU–高效1.2DMIPS/MHz–优化的Thumb2指令集–内存保护单元(MPU)–带有第三方支持的开放式架构–内置调试模块 •操作特性–高达80Mhz系统时钟–单个3.3V电源 •集成内存–带有ECC的448KB总程序闪存–支持闪存EEPROM仿真–带有ECC的24K字节静态RAM(SRAM) •关键外设–高端定时器，多缓冲模数转换器(MibADC)，控制器局域网络(CAN)，多缓冲串行外设接口(MibSPI) •通用TMS470M/570平台架构–系列产品上的一致内存映射–实时中断定时器(RTI)–数字安全装置–矢量中断模块(VIM)–循环冗余校验器(CRC) •基于调频零引脚锁相环路(FMzPLL)的时钟模块–振荡器和PLL时钟模块 •高达49个外设IO引脚–4个专用GIO-带有外部中断 •两个外部时钟前置分频器(ECP)模块–可编程低频外部时钟(ECLK)–一个专用引脚和一个复用ECLK/HET引脚 •通信接口–两个CAN控制器•一个有32个邮箱，另外一个有16个邮箱•邮箱RAM上的奇偶校验–两个多缓冲串行外设接口(MibSPI)•总数为12的芯片选择•64个缓冲器，每个缓冲器上均有奇偶校验–两个通用异步收发器(UART)(SCI)接口•针对本地互连网络（LIN2.1主控模式）的硬件支持 •高端定时器(HET)–多达16个可编程I/O通道–带有奇偶校验的128字高端定时器RAM •16通道10位多缓冲ADC(MibADC)–带有奇偶校验的64字FIFO缓冲器–单一或者连续转换模式–1.55µs最小采样/转换时间–校准模式和自检特性 •片载基于扫描的仿真逻辑电路–IEEE标准1149.1(JTAG)测试-访问端口和边界扫描 •支持的数据包–100引脚塑料四方扁平封装（PZ后缀）–绿色环保/无铅 •可用的开发工具–开发板–CodeComposerStudio集成开发环境(IDE)–HET汇编程序和模拟器–nowFlash™闪存编程工具 •社区资源–TIE2E社区
1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters. 版权©2012,TexasInstrumentsIncorporatedEnglishDataSheet:SPNS159 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 1.1PZ封装视图 ADIN[7]76ADIN[8]77ADIN[9]78ADIN[10]79ADIN[11]80ADIN[12]81ADREFHI82ADREFLO83 VSSAD84VCCAD85ADIN[13]86ADIN[14]87ADIN[15]88PORRST89MIBSPI2ENA90 ENZ91VCC92VSS93VCCIOR94VCCP95ECLK96TEST97RST98FLTP199VSS100 75ADIN[6]74ADIN[5]73ADIN[4]72ADIN[3]71ADIN[2]70ADIN[1]69ADIN[0]68ADEVT67VCC66VSS65VCCIOR64HET[15]/ECLK263HET[14]62HET[13]61HET[12]60HET[11]59HET[10]58HET[9]57HET[8]56HET[7]55HET[6]54HET[5]53HET[4]52VCCIOR51VSS 50HET[3] 49HET[2] 48TRST 47TMS 46TDI 45TDO 44TCK 43 VCCIOR 42VSS 41VCC 40HET[1] 39HET[0] 38CAN2SRX 37CAN2STX 36MIBSPI1SOMI 35MIBSPI1SIMO 34MIBSPI1CLK 33MIBSPI1SCS[0] 32MIBSPI1SCS[1] 31MIBSPI1SCS[2] 30MIBSPI1SCS[3] 29MIBSPI1SCS[4] 28MIBSPI1SCS[5] 27MIBSPI1SCS[6] 26MIBSPI1SCS[7] MIBSPI2SCS[0]1MIBSPI2SCS[1]2MIBSPI2SCS[2]3MIBSPI2SCS[3]
4 GIOA[4]/INT[4]5GIOA[5]/INT[5]
6 CAN1STX7CAN1SRX8 VSS9OSCIN10OSCOUT11 VCC12VSS13VCCIOR14GIOA[6]/INT[6]15GIOA[7]/INT[7]16MIBSPI2CLK17MIBSPI2SIMO18MIBSPI2SOMI19VCCIOR20VSS21LIN1SCI1TX22LIN1SCI1RX23LIN2SCI2TX24LIN2SCI2RX25 图1-
1.TMS470MF04207和TMS470MF03107100引脚PZ封装（顶视图）
2 特性 版权©2012,TexasInstrumentsIncorporated TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 1.2说明 TMS470MF04207/03107器件隶属于德州仪器(TI)的TMS470M汽车级16/32位精简指令集计算机(RISC)微控制器系列。
TMS470M微控制器利用高效率的Cortex™–M316/32位RISC中央处理单元(CPU)提供了高性能，由此实现了很高的指令吞吐量并保持了更加出色的代码效率。
TMS470M器件运用了大端字节序格式，在该格式中，一个字的最高有效字节被存储于编号最小的字节中，而最低有效字节则存储在编号最大的字节中。
高端嵌入式控制应用要求其控制器提供更多的性能并保持低成本。
TMS470M微控制器架构提供了针对这些性能和成本需求的解决方案，并保持了低功耗。
TMS470MF04207/03107器件的组成如下：•16/32位RISCCPU内核•TMS470MF04207高达448K字节的程序闪存（具有SECDEDECC）•TTMS470MF03107高达320K字节的程序闪存（具有SECDEDECC）•具有SECDEDECC的64K字节闪存（用于获得额外的程序空间或进行EEPROM仿真）•高达24K字节的静态RAM(SRAM)（具有SECDEDECC）•实时中断定时器(RTI)•矢量中断模块(VIM)•硬件内置自测试(BIST)校验器，用于SRAM(MBIST)和CPU(LBIST)•64位循环冗余校验器(CRC)•基于调频零引脚锁相环(FMzPLL)的时钟模块（带前置分频器）•两个多缓冲串行外设接口(MibSPI)•两个具有本地互连网络接口(LIN)的UART(SCI)•两个CAN控制器(DCAN)•高端定时器(HET)•外部时钟前置分频器(ECP)模块•一个16通道10位多缓冲ADC(MibADC)•错误信令模块(ESM)•4个专用的通用I/O(GIO)引脚和45个附加外设I/O(100引脚封装) TMS470M内存包括通用SRAM，可支持字节模式、半字模式及字模式的单周期读/写存取。
可以利用ECC对TMS470M器件上的SRAM加以保护。
此项特性运用单错纠正和双错检测电路（SECDED电路）来检测并选择性地校正单位错误以及检测所有的双位错误和某些多位错误。
这是通过将一个用于内存空间的每个64位双字的8位ECC校验和/代码保存在一个单独的ECCRAM内存空间中实现的。
该器件上的闪存是一种非易失性、电可擦且可编程的存储器。
它是采用一个144位宽的数据字（128位，无ECC）和一个64位宽的闪存模块接口实现的。
该闪存在高达28MHz的系统时钟频率条件下运行。
可提供闪存数据线性预读取的流水线模式实现了一个高达80MHz的系统时钟。
TMS470M器件上的增强型实时中断(RTI)模块可选择由振荡器时钟进行驱动。
数字安全装置(DWD)是一个25位的可复位递减计数器，当安全装置计数器终止计数时，该计数器将提供系统复位。
TMS470M器件具有6个通信接口：两个LIN/SCI、两个DCAN和两个MibSPI。
LIN是本地互连网络标准，而且还支持一种SCI模式。
SCI可被用在一个用于CPU与其他采用标准不归零制(NRZ)格式外设之间的异步通信的全双工、串行I/O接口中。
DCAN采用一种串行、多主机通信协议，此协议可高效支持分布式实时控制及高达1兆位每秒(Mbps)的稳健通信速率。
DCAN非常适合于工作于嘈杂和严酷环境中的应用（例如：汽车和工业领域），此类应用需要可靠的串行通信或多路复用线路。
MibSPI为相似的移位寄存器型器件之间的高速通信提供了一种便捷的串行交互方法。
MibSPI提供了标准的SOMI、SIMO和SPI时钟接口以及多达8条芯片选择线路。
版权©2012,TexasInstrumentsIncorporated 特性
3 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 HET是一种先进的智能定时器，可为实时应用提供精密的定时功能。
该定时器为软件控制型，采用一个精简指令集，并具有一个专用的微级机定时器和一个连接的I/O端口。
这种HET可用于比较、捕获或通用型I/O。
它特别适合于那些需要带有复杂和准确的时间脉冲的多种传感器信息和驱动传动器的应用。
TMS470MHET外设包含“异或(XOR)共享”功能。
该功能允许对两个相邻的HET高分辨率通道进行“异或”运算，从而可以输出一个小于标准HET的脉冲。
TMS470M器件具有一个10位分辨率的采样及保持MibADC。
可利用软件对每个MibADC通道进行分组，以用于顺序转换序列。
有三个单独的分组，它们均可以由一个外部事件触发。
每个序列可在被触发时执行一次转换，或者通过配置以执行连续转换模式。
调频零引脚锁相环(FMzPLL)时钟模块包含一个锁相环、一个时钟监视器电路、一个时钟启用电路和一个前置分频器。
FMzPLL的功能是将外部频率基准倍频至一个较高的频率，以供内部使用。
FMzPLL提供了全局时钟模块(GCM)的输入。
GCM模块接着向所有其他的TMS470M器件模块提供系统时钟(HCLK)、实时中断时钟(RTICLK)、CPU时钟(GCLK)、HET时钟(VCLK2)、DCAN时钟(AVCLK1)及外设接口时钟(VCLK)。
另外，TMS470MF04207/TMS470MF03107器件还具有两个外部时钟前置分频器(ECP)模块，该模块在被启用时将输出一个连续外部时钟(ECLK)。
ECLK1频率是外设接口时钟(VCLK)频率的一个用户可编程比值。
可以选择第二个ECLK输出来取代HET15输出。
它与ECLK1共用同一个信源时钟，但可以针对一个产生自ECLK1的单独输出频率进行独立设置。
错误信令模块(ESM)在器件内部提供了一个用于错误报告的共用位置，从而实现了高效的错误检查和识别。
4 特性 版权©2012,TexasInstrumentsIncorporated 1.3功能方框图图1-2显示了TMS470M器件的功能方框图。
TMS470MF04207/TMS470MF03107 LBIST JTAG-DP nVIC Cortex™M3 withMPU IDSYS M3VIM VCCPFLTP1 BMM BMM Flash RAM PSA A2V Upto384KB Upto24KB w/ECC w/ECC Flash64KBw/ECC MBIST OSCIN1OSCOUT1 VCCIORENZ VCCVCCVCCVCC OSCPLLCLKMonitor 1.5-VP-ChVREG VCCOUT Passgate1 Passgate2 Passgate3 Passgate4 PCR FlashWrapper RAMWrapper RTI/DWD TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 ICEPICK BoundaryScan HET128Words w/ParityESM SYS LIN/SCI1 LIN/SCI2 MibSPI164Words/16TGsw/Parity MibSPI264Words/8TGsw/Parity TMSTCKTRSTTDITDO HET[15:0] RSTPORRSTTESTECLKLIN/SCI1TXLIN/SCI1RXLIN/SCI2TXLIN/SCI2RXMIBSPI1SIMOMIBSPI1SOMIMIBSPI1CLKMIBSPI1SCS[7:0]MIBSPI2SIMOMIBSPIP2SOMIMIBSPI2CLKMIBSPI2SCS[3:0]MIBSPI2ENA ADC64Wordsw/Parity DCAN116Mailboxes w/Parity DCAN232Mailboxes w/Parity GIO ADIN[15:0]ADEVTVCCADVSSADADREFHIADREFLOCANS1RXCANS1TX CANS2RXCANS2TX GIOOA[7:4]/INTA[7:4] 图1-
2.TMS470M系列方框图 版权©2012,TexasInstrumentsIncorporated 特性
5 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 1.4术语和首字母缩略词 术语和首字母缩略词A2V ADCAHBBMM CRCDAPDCANDWDECCESMGIOHETICEPICK JTAGJTAG-DP LBISTLIN M3VIMMBISTMibSPIMPUNVICOSCPCR PLLPSARTISCISECDEDSTCSYSVBUSVBUSPVREG 表1-
1.术语和首字母缩略词 描述AHB至VBUSP桥接 模数转换器高级高性能总线总线矩阵主控 循环冗余校验控制器调试访问端口控制器局域网数字安全装置错误校正码错误信令模块通用输入/输出高端定时器 处于电路仿真TAP（测试访问端口）选择模块 联合测试访问组JTAG调试端口 逻辑内置自检本地互连网络Cortex-M3矢量中断管理器存储器内置自检多缓冲串行外设接口 保护单元嵌套矢量中断控制器 振荡器外设中心资源 锁相环路并行签名分析 实时中断串行通信接口单一错误校正和双错误校正自检控制器 系统模块虚拟总线虚拟管道型总线电压稳压器 注释A2V桥接提供私有TIVBUSP和TMS470M平台器件中ARM AHB总线间的内存接口。
M3内核的部件 BMM提供不同总线受控模块到不同总线主控模块的连接性。
如果没有发生资源冲突或者如果主控模块在仲裁过程中保持并行的 话，来自不同总线模块的访问可并行执行。
DAP是一个ARM调试接口的工具。
ICEPick能够连接或者隔离一个模块级TAP到一个更高级芯片TAP的数据通信。
ICEPick设计时充分考虑了仿真和测试需 要。
负责测试访问端口的IEEE委员会JTAG-DP包含一个调试端口状态机(JTAG)，此状态机控制JTAG-DP运行，包括控制扫描链路接口，此接口提供到JTAGDP的外部物理接口。
它基于JTAGTAP状态机，请见IEEE 标准1149.1-2001。
测试M3CPU的完整性 测试SRAM的完整性 M3内核的部件 包括CBA（通用总线架构）的协议中的一个包括CBA（通用总线架构）的协议中的一个
6 特性 版权©2012,TexasInstrumentsIncorporated 1特性.........................................................11.1PZ封装视图.........................................21.2说明..................................................31.3功能方框图...........................................51.4术语和首字母缩略词.................................6 2DeviceOverview........................................82.1MemoryMapSummary..............................92.2TerminalFunctions.................................142.3DeviceSupport.....................................18 3DeviceConfigurations................................203.1Reset/AbortSources...............................203.2LockupResetModule..............................213.3ESMAssignments..................................213.4InterruptPriority(M3VIM)..........................223.5MibADC.............................................233.6MibSPI..............................................243.7JTAGID............................................253.8ScanChains........................................253.9AdaptiveImpedance4mAIOBuffer...............253.10Built-InSelfTest(BIST)Features..................293.11DeviceIdentificationCodeRegister................32 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 3.12DevicePartNumbers...............................334DeviceOperatingConditions.......................34 4.1AbsoluteMaximumRatingsOverOperatingFree- AirTemperatureRange,QVersion................344.2DevicemendedOperatingConditions......34 4.3ElectricalCharacteristicsOvermendedOperatingFree-AirTemperatureRange,QVersion ......................................................35 5PeripheralInformationandElectrical Specifications..........................................365.1RSTandPORRSTTimings........................365.2PLLandClockSpecifications......................395.3SPInMasterModeTimingParameters............505.4SPInSlaveModeTimingParameters..............545.5CANController(DCANn)ModeTimings...........585.6High-EndTimer(HET)Timings....................585.7Multi-BufferedA-to-DConverter(MibADC).........596RevisionHistory.......................................637MechanicalData.......................................647.1ThermalData.......................................647.2PackagingInformation..............................64 Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 内容
7 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 2DeviceOverview TheTMS470MF04207/03107deviceisaTMS470MPlatformArchitectureimplementedinF035130-nmTItechnology.Table2-1identifiesallthecharacteristicsoftheTMS470MF04207/03107deviceexcepttheSYSTEMandCPU,whicharegeneric. Table2-
1.DeviceCharacteristics CHARACTERISTICS DEVICEDESCRIPTIONTMS470MF04207/03107 COMMENTSFORTMS470M MEMORY INTERNALMEMORY Pipeline/Non-Pipeline2Bankswithupto448K-Byte FlashwithECCUpto24K-ByteSRAMwithECC CRC,1-channel Flashispipeline-capable PERIPHERALS Forthedevice-specificinterruptpriorityconfigurations,seeTable3-
4.Fortheperipheraladdressrangesandtheirperipheralselects,seeTable2-
7. CLOCK FMzPLL Frequency-modulatedzero-pinPLLhasnoexternalloopfilterpins. GENERAL-PURPOSEI/Os 4I/O TheGIOAporthasuptofour(4)externalpinswithexternalinterruptcapability. LIN/SCI 2LIN/SCI DCAN 2DCAN Eachwith16/32mailboxes,respectively. MibSPI 2MibSPI OneMibSPIwitheightchipselectpins,16transfergroups,anda64wordbufferwithparity.AsecondMibSPIwithfourchipselectpins,1enablepin,8transfergroups,anda64wordbufferwithparity. HETwithXORShare 16I/O Thehigh-resolution(HR)SHAREfeatureallowseven-numberedHRpinstosharethenexthigherodd-numberedHRpinstructures.ThisHRsharingisindependentofwhetherornottheoddpinisavailableexternally.Ifanoddpinisavailableexternallyandshared,thentheoddpincanonlybeusedasageneral-purposeI/O.HETRAMwithparitycheckingcapability. HETRAM 128-InstructionCapacity MibADC 10-bit,16-channel64-wordFIFO MibADCRAMincludesparitysupport. COREVOLTAGE 1.55V Thecorevoltageissuppliedandregulatedbythedevice'sinternalvoltageregulator.Thereisnotneedforanexternallysuppliedcorevoltage. I/OVOLTAGE 3.3V PINS 100 Availableina100-pinpackage. PACKAGE PZ(100pin) The100-pinpackagedesignatorisPZ.
8 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 2.1MemoryMapSummary2.1.1MemoryMap Figure2-1andFigure2-2showtheTMS470MF04207andTMS470MF03107memorymaps. 0xFFFFFFFF0xFFF800000xFFF7FFFF 0xFF0000000xFEFFFFFF0xFE000000 SYSTEMModulePeripheralsPSA 0x08405FFF0x08400000 RAM-ECC 0x08105FFF0x08100000 RAM-CLRSpace(A)(24KB) 0x08085FFF0x08080000 RAM-SETSpace(A)(24KB) 0x08005FFF0x08000000 0x0047FFFF0x004400000x0042FFFF0x004000000x0008FFFF 0x000800000x0005FFFF RAM(24KB)FLASH-ECC(Bank1)FLASH-ECC(Bank0)FLASH(64KB-Bank1) 0x00000000 FLASH(384KB-Bank0)
A.TheRAMsupportsbitessoperationwhichallowsset/cleartodedicatedbitswithoutdisturbingtheotherbits;fordetaileddescription,seetheArchitectureSpecification. Figure2-
1.TMS470MF04207MemoryMap Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview
9 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 0xFFFFFFFF0xFFF800000xFFF7FFFF 0xFF0000000xFEFFFFFF0xFE000000 SYSTEMModulePeripheralsPSA 0x08403FFF0x08400000 RAM-ECC 0x08103FFF0x08100000 RAM-CLRSpace(A)(16KB) 0x08083FFF0x08080000 RAM-SETSpace(A)(16KB) 0x08003FFF0x08000000 0x00447FFF0x004400000x0041FFFF0x00400000 0x0008FFFF0x000800000x0003FFFF RAM(16KB)FLASH-ECC(Bank1)FLASH-ECC(Bank0)FLASH(64KB-Bank1) FLASH(256KB-Bank0) 0x00000000A.TheRAMsupportsbitessoperationwhichallowsset/cleartodedicatedbitswithoutdisturbingtheotherbits;for detaileddescription,seetheArchitectureSpecification. Figure2-
2.TMS470MF03107MemoryMap 10 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 2.1.2MemorySelects MemoriesintheTMS470Mdevicesarelocatedatfixedaddresses.Table2-2throughTable2-7detailthemappingofthememoryregions. Table2-
2.TMS470MF04207-SpecificMemoryFrameAssignment MEMORYFRAMENAME STARTADDRESS ENDINGADDRESS MEMORYTYPE ACTUALMEMORY nCS0
(1) 0x000000000x00080000 0x0005FFFF0x0008FFFF FlashFlash 384KBytes64KBytes RAM-CLR 0x08100000 0x08105FFF InternalRAM 24KBytes RAM-SET 0x08080000 0x08085FFF InternalRAM 24KBytes CSRAM0
(1) 0x080000000x08400000 0x08005FFF0x08405FFF InternalRAMInternalRAM-ECC 24KBytes24KBytes
(1)Additionaladdressmirroringcouldbepresentresultingininvalidbutaddressablelocationsbeyondthoselistedabove.TImendstheuseoftheMPUforprotectingesstoaddressesoutsidetheintendedrangeofuse. Table2-
3.TMS470MF03107-SpecificMemoryFrameAssignment MEMORYFRAMENAME STARTADDRESS ENDINGADDRESS MEMORYTYPE ACTUALMEMORY nCS0
(1) 0x000000000x00080000 0x0003FFFF0x0008FFFF FlashFlash 256KBytes64KBytes RAM-CLR 0x08100000 0x08103FFF InternalRAM 16KBytes RAM-SET 0x08080000 0x08083FFF InternalRAM 16KBytes CSRAM0
(1) 0x080000000x08400000 0x08003FFF0x08403FFF InternalRAMInternalRAM-ECC 16KBytes16KBytes
(1)Additionaladdressmirroringcouldbepresentresultingininvalidbutaddressablelocationsbeyondthoselistedabove.TImendstheuseoftheMPUforprotectingesstoaddressesoutsidetheintendedrangeofuse. Table2-
4.MemoryInitializationandMBIST CONNECTINGMODULE ADDRESSRANGEBASEADDRESSENDINGADDRESS MEMORYINITIALIZATIONCHANNEL MBISTCONTROLLERENABLECHANNEL SystemRAM(TMS470MF04207) 0x08000000 0x08005FFF
0 0 SystemRAM(TMS470MF03107) 0x08000000 0x08003FFF
0 0 MibSPI1RAM 0xFF0E0000 0xFF0FFFFF
1 MibSPI2RAM 0xFF0C0000 0xFF0DFFFF
2 1or2
(1) DCAN1RAM 0xFF1E0000 0xFF1FFFFF
3 DCAN2RAM 0xFF1C0000 0xFF1DFFFF
4 3or4
(1) ADCRAM 0xFF3E0000 0xFF3FFFFF
5 5 HETRAM 0xFF460000 0xFF47FFFF NotAvailable
6 STCROM NotApplicable NotApplicable NotApplicable
7
(1)TherearesingleMBISTcontrollersforbothMibSPIRAMsandbothDCANRAMs.TheMBISTcontrollerforbothMibSPIRAMsismappedtochannels1and2andtheMBISTcontrollerforbothDCANRAMsismappedtochannels3and4.MBISTonthesemodulescanbeinitiatedbyselectingoneofthe2channelsorboth. Table2-
5.PeripheralMemoryChipSelectAssignment CONNECTINGMODULE MibSPI1RAMMibSPI2RAMDCAN1RAMDCAN2RAM ADDRESSRANGE BASEADDRESSENDINGADDRESS 0xFF0E0000 0xFF0FFFFF 0xFF0C0000 0xFF0DFFFF 0xFF1E0000 0xFF1FFFFF 0xFF1C0000 0xFF1DFFFF PERIPHERALSELECTS PCS[7]PCS[6]PCS[14]PCS[15] Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview 11 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table2-
5.PeripheralMemoryChipSelectAssignment(continued) CONNECTINGMODULE ADCRAMHETRAM ADDRESSRANGE BASEADDRESSENDINGADDRESS 0xFF3E0000 0xFF3FFFFF 0xFF460000 0xFF47FFFF PERIPHERALSELECTS PCS[31]PCS[35] NOTEAllusedperipheralmemorychipselectsshoulddecodedowntothesmallestpossibleaddressforthisparticularperipheralconfiguration,startingfrom4kBupwards.Unusedaddressesshouldgenerateanillegaladdresserrorwhenessed. Table2-
6.SystemPeripheralRegisters FRAMENAME PSAFlashWrapperRegisters PCRRegisterSystemFrame2Registers CPUSTC(LBIST)ESMRegister RAMECCRegisterRTIRegisterVIMRegister SystemRegisters ADDRESSRANGE FRAMESTARTADDRESSFRAMEENDINGADDRESS 0xFE000000 0xFEFFFFFF 0xFFF87000 0xFFF87FFF 0xFFFFE000 0xFFFFE0FF 0xFFFFE100 0xFFFFE1FF 0xFFFFE400 0xFFFFE4FF 0xFFFFF500 0xFFFFF5FF 0xFFFFF900 0xFFFFF9FF 0xFFFFFC00 0xFFFFFCFF 0xFFFFFE00 0xFFFFFEFF 0xFFFFFF00 0xFFFFFFFF Table2-
7.PeripheralSelectMapwithAddressRange CONNECTINGMODULE MibSPI2MibSPI1LIN/SCI1LIN/SCI2DCAN2DCAN1 ADCGIOHET BASEADDRESS 0xFFF7F6000xFFF7F4000xFFF7E5000xFFF7E4000xFFF7DE000xFFF7DC000xFFF7C0000xFFF7BC000xFFF7B800 ENDADDRESS 0xFFF7F7FF0xFFF7F5FF0xFFF7E5FF0xFFF7E4FF0xFFF7DFFF0xFFF7DDFF0xFFF7C1FF0xFFF7BCFF0xFFF7B8FF PERIPHERALSELECTSPS[2] PS[6] PS[8]PS[15]PS[16]PS[17] 2.1.3FlashMemory Wheninpipelinemode,theFlashoperateswithasystemclockfrequencyofupto80MHz(versusasystemclockinnon-pipelinemodeofupto28MHz).Flashinpipelinemodeiscapableofessing128bitwordsandprovidesfour32-bitpipelinedwordstotheCPU. 12 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 NOTE
1.Afterasystemreset,pipelinemodeisdisabled[FRDCNTL[2:0]is000b,seetheFlashchapterintheTMS470MSeriesTechnicalReferenceManual(literaturenumberSPNU495)].Inotherwords,thedevicepowersupesoutofresetinnonpipelinemode.
2.Theflashexternalpumpvoltage(VCCP)isrequiredforalloperations(program,erase,andread). 2.1.4FlashProgramandErase TheTMS470MF04207/TMS470MF03107devicesflashcontainone384/256K-bytememoryarray(orbank)andone64K-bytebankforatotalofupto12sectors.Table2-8andTable2-9showtheTMS470MF04207andTMS470MF03107flashmemorybanksandsectors. Theminimumsizeforaneraseoperationisonesector.Themaximumsizeforaprogramoperationisone32-bitword. Table2-
8.TMS470MF04207FlashMemoryBanksandSectors SECTORNO. SEGMENT LOWADDRESS HIGHADDRESS
0 16k 0x00000000 0x00003FFF
1 16k 0x00004000 0x00007FFF
2 32k 0x00008000 0x0000FFFF
3 64k 0x00010000 0x0001FFFF
4 64k 0x00020000 0x0002FFFF
5 64k 0x00030000 0x0003FFFF
6 64k 0x00040000 0x0004FFFF
7 64k 0x00050000 0x0005FFFF
0 16k 0x00080000 0x00083FFF
1 16k 0x00084000 0x00087FFF
2 16k 0x00088000 0x0008BFFF
3 16k 0x0008C000 0x0008FFFF
(1)Bank1canbeusedaseitherEEPROMemulationspaceorasprogramspace. MEMORYARRAYS(ORBANKS) BANK0(384KBytes) BANK1
(1)(64KBytes) Table2-
9.TMS470MF03107FlashMemoryBanksandSectors SECTORNO. SEGMENT LOWADDRESS HIGHADDRESS
0 16k 0x00000000 0x00003FFF
1 16k 0x00004000 0x00007FFF
2 32k 0x00008000 0x0000FFFF
3 64k 0x00010000 0x0001FFFF
4 64k 0x00020000 0x0002FFFF
5 64k 0x00030000 0x0003FFFF
0 16k 0x00080000 0x00083FFF
1 16k 0x00084000 0x00087FFF
2 16k 0x00088000 0x0008BFFF
3 16k 0x0008C000 0x0008FFFF
(1)Bank1canbeusedaseitherEEPROMemulationspaceorasprogramspace. MEMORYARRAYS(ORBANKS) BANK0(256KBytes) BANK1
(1)(64KBytes) Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview 13 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 2.2TerminalFunctions Theterminalfunctionstable(Table2-10)identifiesthepinnames,theassociatedpinnumbers,inputvoltage,outputvoltage,whetherthepinhasanyinternalpullup/pulldownresistorsandafunctionalpindescription.TheTMS470MF04207andTMS470MF03107deviceshavethesamepinout. TERMINAL NAME 100PIN HET[0] 39 HET[1] 40 HET[2] 49 HET[3] 50 HET[4] 53 HET[5] 54 HET[6] 55 HET[7] 56 HET[8] 57 HET[9] 58 HET[10] 59 HET[11] 60 HET[12] 61 HET[13] 62 HET[14] 63 HET[15]/ECLK2 64 CAN1STX
7 CAN1SRX
8 CAN2STX 37 CAN2SRX 38 GIOA[4]/INT[4]
5 GIOA[5]/INT[5]
6 GIOA[6]/INT[6] 15 GIOA[7]/INT[7] 16 Table
2-10.TerminalFunctions INPUTVOLTAGE
(1)
(2) OUTPUTCURRENT
(3) IPU/IPD
(4) HIGH-ENDTIMER(HET) DESCRIPTION 3.3-VI/O Adaptiveimpedance4 mA ProgrammableIPD(100µA) Timerinputcaptureorpare.TheHET[15:0]applicablepinscanbeprogrammedasgeneral-purposeinput/output(GIO)pins. Thehigh-resolution(HR)SHAREfeatureallowsevenHRpinstosharethenexthigheroddHRpinstructure.ThenexthigheroddHRpinstructureisalwaysimplemented,evenifthenexthigheroddHRpadand/orpinitselfisnot. Note:HET[15]ismuxedwithECLK2output.IfECLK2outputisenabled(throughSYSPC1registerat0xFFFFFF00),ECLK2isoutputonthispinandHET[15]esaninternalonlyHETchannel. Note:ECLK2sourceselectmustbeprogrammedthesameasECLK1duetodevicespecificimplementationdetails. Note:ECLK2isenabledandECLK2dividerisprogrammedthroughECPcontrolregister1inSystemFrame2Registers(0xFFFFE128). 3.3-VI/O3.3-VI/O3.3-VI/O CANCONTROLLER1(DCAN1) Adaptiveimpedance4 mA ProgrammableIPU(100µA) DCAN1transmitpinorGIOpin.DCAN1receivepinorGIOpin. CANCONTROLLER2(DCAN2) Adaptiveimpedance4 mA ProgrammableIPU(100µA) DCAN2transmitpinorGIOpinDCAN2receivepinorGIOpin GENERAL-PURPOSEI/O(GIO) Adaptiveimpedance4 mA ProgrammableIPD(100µA) General-purposeinput/outputpins.Theyareinterrupt-capablepins.
(1)PWR=power,GND=ground,REF=referencevoltage,NC=noconnect
(2)AllI/Opins,exceptRST,areconfiguredasinputswhilePORRSTislowandimmediatelyafterPORRSTgoeshigh.
(3)TheTMS470Mdeviceutilizesadaptiveimpedance4mAbuffersthatdefaulttoanadaptiveimpedancemodeofoperation.Asafail-safe, theadaptiveimpedancefeaturesofthebuffermaybedisabledandrevertthebuffertoastandardbuffermode.
(4)IPD=internalpulldown,IPU=internalpullup(allinternalpullupsandpulldownsareinactiveoninputpinswhenPORRSTisasserted) 14 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table2-10.TerminalFunctions(continued) TERMINAL NAME 100PIN INPUTVOLTAGE
(1)
(2) OUTPUTCURRENT
(3) IPU/IPD
(4) DESCRIPTION MIBSPI1CLKMIBSPI1SCS[0]MIBSPI1SCS[1]MIBSPI1SCS[2]MIBSPI1SCS[3]MIBSPI1SCS[4]MIBSPI1SCS[5]MIBSPI1SCS[6]MIBSPI1SCS[7]MIBSPI1SIMOMIBSPI1SOMI MibSPI2CLKMibSPI2SCS[0]MibSPI2SCS[1]MibSPI2SCS[2]MibSPI2SCS[3]MibSPI2ENAMibSPI2SIMO[0] MibSPI2SOMI[0] LIN/SCI1RXLIN/SCI1TXLIN/SCI2RXLIN/SCI2TX ADEVT MULTI-BUFFEREDSERIALPERIPHERALINTERFACE1(MIBSPI1) 34 MIBSPI1clock.MIBSPI1CLKcanbeprogrammed asaGIOpin. 33 32 31 30 MIBSPI1slavechipselect.MIBSPI1SCS[7:0]can 29 Adaptive ProgrammablebeprogrammedasaGIOpins. 283.3-VI/OimpemdaAnce4IPU(100µA) 27 26 35 MIBSPI1datastream.Slavein/masterout. MIBSPI1SIMOcanbeprogrammedasaGIOpin. 36 MIBSPI1datastream.Slaveout/masterin. MIBSPI1SOMIcanbeprogrammedasaGIOpin. MULTI-BUFFEREDSERIALPERIPHERALINTERFACE2(MibSPI2) 17 MibSPI2clock.MibSPI2CLKcanbeprogrammed asaGIOpin.
1 2 MibSPI2slavechipselectMibSPI2SCS[3:0]canbe
3 programmedasGIOpins.
4 Adaptive 90 3.3-VI/O impedance4 ProgrammableIPU(100µA) MibSPI2enablepin.MibSPI2ENAcanbe mA programmedasaGIOpin. 18 MibSPI2datastream.Slavein/masterout. MibSPI2SIMOpinscanbeprogrammedasaGIO pins. 19 MibSPI2datastream.Slaveout/masterin. MibSPI2SOMIpinscanbeprogrammedasGIO pins. LOCALINTERCONNECTNETWORK/SERIALCOMMUNICATIONSINTERFACE(LIN/SCI) 23 LIN/SCI1datareceive.Canbeprogrammedasa Adaptive ProgrammableGIOpin. 22 3.3-VI/O impedance4mA IPU(100µA)LIN/SCI1datatransmit.Canbeprogrammedasa GIOpin. 25 LIN/SCI2datareceive.Canbeprogrammedasa Adaptive ProgrammableGIOpin. 24 3.3-VI/O impedance4mA IPU(100µA)LIN/SCI2datatransmit.Canbeprogrammedasa GIOpin. MULTI-BUFFEREDANALOG-TO-DIGITALCONVERTER(MIBADC) 68 3.3-VI/O Adaptive ProgrammableMibADCeventinput.CanbeprogrammedasaGIO impedance4IPD(100µA)pin. mA Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview 15 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 TERMINAL NAME 100PIN ADIN[0] 69 ADIN[1] 70 ADIN[2] 71 ADIN[3] 72 ADIN[4] 73 ADIN[5] 74 ADIN[6] 75 ADIN[7] 76 ADIN[8] 77 ADIN[9] 78 ADIN[10] 79 ADIN[11] 80 ADIN[12] 81 ADIN[13] 86 ADIN[14] 87 ADIN[15] 88 ADREFHI 82 ADREFLO 83 VCCAD 85 VSSAD 84 OSCIN 10 OSCOUT 11 PORRST 89 RST 98 ECLK 96 TCK 44 TDI 46 TDO 45 TMS 47 TRST 48 Table
2-10.TerminalFunctions(continued) INPUTVOLTAGE
(1)
(2) OUTPUTCURRENT
(3) IPU/IPD
(4) DESCRIPTION 3.3V MibADCanaloginputpins. 3.3-VREFGNDREF3.3-VPWR GND1.55-VI1.55-VO3.3-VI 3.3-VI/O 3.3-VI/O 3.3-VI 3.3-VI/O 3.3-VI OSCILLATOR(OSC) SYSTEMMODULE(SYS)IPD(100µA) Adaptiveimpedance4 mA IPU(100µA) Adaptiveimpedance4 mA ProgrammableIPD(100µA) TEST/DEBUG(T/D) IPD(100µA) IPU(100µA) Adaptiveimpedance4 mA IPD(100µA) IPU(100µA)IPD(100µA) MibADCmodulehigh-voltagereferenceinput.MibADCmodulelow-voltagereferenceinput.MibADCanalogsupplyvoltage.MibADCanaloggroundreference. Crystalconnectionpinorexternalclockinput.Externalcrystalconnectionpin. Inputmasterchippower-upreset.ExternalVCCmonitorcircuitrymustassertapower-onreset.Bidirectionalreset.Theinternalcircuitrycanassertareset,andanexternalsystemresetcanassertadevicereset.Onthispin,theoutputbufferisimplementedasanopendrain(driveslowonly).Toensureanexternalresetisnotarbitrarilygenerated,TImendsthatanexternalpullupresistorbeconnectedtothispin.Bidirectionalpin.ECLKcanbeprogrammedasaGIOpin. Testclock.TCKcontrolsthetesthardware(JTAG).Testdatainpin.TDIinputsserialdatatothetestinstructionregister,testdataregister,andprogrammabletestaddress(JTAG).Testdataoutpin.TDOoutputsserialdatafromthetestinstructionregister,testdataregister,identificationregister,andprogrammabletestaddress(JTAG).SerialinputpinforcontrollingthestateoftheCPUtestessport(TAP)controller(JTAG).TesthardwareresettoTAP.IEEEStandard1149-1(JTAG)Boundary-ScanLogic. 16 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TERMINAL NAME 100PIN TEST 97 ENZ 91 FLTP1 99 VCCP1 95 VCCP2 95 VCC 12 41 67 92 VCCIOR 14 20 43 52 65 94 VSS
9 13 21 42 51 66 93 100 TMS470MF04207
TMS470MF03107 ZHCS061C–JANUARY2012 Table2-10.TerminalFunctions(continued) INPUTVOLTAGE
(1)
(2) OUTPUTCURRENT
(3) IPU/IPD
(4) DESCRIPTION 3.3-VI IPD(100µA) Testenable.Reservedforinternaluseonly.TImendsthatthispinbeconnectedtogroundorpulleddowntogroundbyanexternalresistor. Enables/disablestheinternalvoltageregulator. 0V-Enablesinternalvoltageregulator. 3.3-VI IPD(100µA)3.3V-Disablesinternalvoltageregulator. 3.3-VPWR1.55-VPWR Note:TheENZpinisprovidedtofacilitatetestingacrossthecorevoltagerangeandisnotintendedfordisablingtheonchipvoltageregulatorduringapplicationuse. FLASH FlashTestPad1pin.Forproperoperation,thispinmustconnectonlytoatestpadornotbeconnectedatall[noconnect(NC)].ThetestpadmustnotbeexposedinthefinalproductwhereitmightbesubjectedtoanESDevent. Flashexternalpumpvoltage(3.3V).ThispinisrequiredforbothFlashreadandFlashprogramanderaseoperations.VCCP1andVCCP2aredoublebondedtothesamepin. SUPPLYVOLTAGECORE(1.55V) VregoutputvoltagewhenVregisenabled.VCCinputwhenVregisdisabled. SUPPLYVOLTAGEDIGITALI/OANDREGULATOR(3.3V) 3.3-VPWR DigitalI/Oandinternalregulatorsupplyvoltage. SUPPLYGROUND GND DigitalI/Oandcoresupplygroundreference. Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview 17 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 2.3DeviceSupport 2.3.1DeviceandDevelopment-SupportToolNomenclature Todesignatethestagesintheproductdevelopmentcycle,TIassignsprefixestothepartnumbersofalldevicesandsupporttools.mercialfamilymemberhasoneofthreeprefixes:TMX,TMP,orTMS(e.g.,TMS470MF04207).TexasInstrumentsmendstwoofthreepossibleprefixdesignatorsforitssupporttools:TMDXandTMDS.Theseprefixesrepresentevolutionarystagesofproductdevelopmentfromengineeringprototypes(TMX/TMDX)throughfullyqualifiedproductiondevices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimentaldevicethatisnotnecessarilyrepresentativeofthefinaldevice'selectricalspecifications. TMP Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthaspletedqualityandreliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproductthathasnotpletedTexasInstrumentsinternalqualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMXandTMPdevicesandTMDXdevelopment-supporttoolsareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMSdevicesandTMDSdevelopment-supporttoolshavebeencharacterizedfully,andthequalityandreliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies. Predictionsshowthatprototypedevices(TMXorTMP)haveagreaterfailureratethanthestandardproductiondevices.TexasInstrumentsmendsthatthesedevicesnotbeusedinanyproductionsystembecausetheirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesaretobeused. TIdevicenomenclaturealsoincludesasuffixwiththedevicefamilyname.Thissuffixindicatesthepackagetype(forexample,PZ),thetemperaturerange(forexample,"Blank"ismercialtemperaturerange),andthedevicespeedrangeinmegahertz. Figure2-3illustratesthenumberingandsymbolnomenclaturefortheTMS470Mfamily. 18 DeviceOverview Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 FullPartNumber TMS470MF04
2 07B SPZQQ1R OrderablePartNumberS
4 MF04
2 07
B SPZQQ1R Prefix:TMS=TMSQualifiedP=TMPPrototypeX=TMXSamples CoreTechnology:4=470CortexM3 Architecture:MF=M3Flash FlashMemorySize:04=448KBytes03=320KBytes RAMMemorySize:2=24KBytes1=16KBytes PeripheralConfiguration: DieRevision:Blank=InitialDieA=FirstDieRevisionB=SecondDieRevision Technology/CoreVoltage:S=F035(130nm),1.5-VNominalCoreVoltage PackageType:PZ=100-PinQFPPackage(Green) TemperatureRange:Q=-40°Cto+125°
C QualityDesignator:Q1=Automotive ShippingOptions:R=TapeandReel NOTE:Thepartnumbergivenaboveisforillustrativepurposesonlyanddoesnotnecessarilyrepresentthespecificpartnumberorsiliconrevisiontowhichthisdocumentapplies. Figure2-
3.TMS470MDeviceNumberingConventions Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceOverview 19 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 3DeviceConfigurations 3.1Reset/AbortSourcesResets/abortsarehandledasshowninTable3-
1.Table3-
1.Reset/AbortSources ERRORSOURCE 1)CPUTRANSACTIONSPrecisewriteerror(NCNB/StronglyOrdered)Precisereaderror(NCB/DeviceorNormal)Imprecisewriteerror(NCB/DeviceorNormal)Externalimpreciseerror(Illegaltransactionwithokresponse)Illegalinstruction SYSTEMMODE User/PrivilegeUser/PrivilegeUser/PrivilegeUser/Privilege User/Privilege M3LockupMPUessviolation User/PrivilegeUser/Privilege 2)SRAMECCsingleerror(correctable)ECCdoubleerror(uncorrectable) User/PrivilegeUser/Privilege 3)FLASHWITHECCECCsingleerror(correctable)ECCdoubleerror(uncorrectable) User/PrivilegeUser/Privilege 8)HETHETMemoryparityerror User/Privilege 9)MIBSPIMibSPI1memoryparityerrorMibSPI2memoryparityerror User/PrivilegeUser/Privilege 10)MIBADCMemoryparityerror User/Privilege 11)DCAN/CANDCAN1memoryparityerrorDCAN2memoryparityerror User/PrivilegeUser/Privilege 13)PLLPLLsliperror User/Privilege 14)CLOCKMONITORClockmonitorinterrupt User/Privilege 19)VOLTAGEREGULATOR outofrange n/a 20)CPUSELFTEST(LBIST)CPUSelftest(LogicBIST)error User/Privilege 21)ERRORSREFLECTEDINTHESYSESRREGISTER Power-UpReset/Vregoutofvoltage
(2) n/a ERRORRESPONSE PreciseAbort(CPU)PreciseAbort(CPU)ImpreciseAbort(CPU) ESMUndefinedInstructionTrap (CPU)
(1)ESM=>NMIAbort(CPU) ESMESM=>NMI ESMESM=>NMI ESM ESMESM ESM ESMESM ESM ESM Reset ESM Reset ESMHOOKUP,GROUP.CHANNEL n/an/an/a2.17n/a2.16n/a 1.262.6 1.62.4 1.7 1.171.18 1.19 1.211.23 1.10 1.11 n/a 1.27 n/a
(1)TheundefinedinstructiontrapisNOTdetectedoutsideoftheCPU.ThetrapistakenonlyifthecodereachestheexecutestageoftheCPU.
(2)Bothapower-onresetandVregout-of-rangeresetareindicatedbythePORSTbitintheSYSESRregister. 20 DeviceConfigurations Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table3-
1.Reset/AbortSources(continued) ERRORSOURCE SYSTEMMODE ERRORRESPONSE Oscillatorfail/PLLslip
(3)M3Lockup/LRMWatchdogtimelimitexceededCPUResetSoftwareResetExternalReset n/a Reset n/a Reset n/a Reset n/a Reset n/a Reset n/a Reset
(3)Oscillatorfail/PLLslipcanbeconfiguredinthesystemregister(SYS.PLLCTL1)togenerateareset. ESMHOOKUP,GROUP.CHANNEL n/an/an/an/an/an/a 3.2LockupResetModule Thelockupresetmodule(LRM)isimplementedmunicatealockupconditionbythecore.TheLRMprovidesasmallwatchdogtimerwhichcangenerateasystemresetincasealockupconditionthatisidentifiedbythecorecannotbeclearedbysoftware. 3.3ESMAssignments TheESMmoduleisintendedformunicationcriticalsystemfailuresinacentrallocation.Theerrorindicationisbyanerrorinterruptwhenthefailureisrecognizedfromanydetectionunit.TheESMmoduleconsistofthreeerrorgroupswith32inputseach.ThegenerationoftheinterruptsisshowninTable3-
2.ESMassignmentsarelistedinTable3-
3. Table3-
2.ESMGroups ERRORGROUPGroup1Group2Group3 INTERRUPT,LEVELmaskable,low/highnon-maskable,high NotUsed Table3-
3.ESMAssignments ERRORSOURCESGROUP1 ReservedFlash-ECCSingleBitHETmemoryparityerror ReservedPLLSlipErrorClockMonitorinterrupt ReservedMibSPI1memoryparityerrorMibSPI2memoryparityerrorMibADCmemoryparityerror ReservedDCAN1memoryparityerror ReservedDCAN2memoryparityerror ReservedSRAM-singlebitCPULBIST-selftesterror CHANNEL 0-5678-91011 12-1617181920212223 24-252627 Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceConfigurations 21 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table3-
3.ESMAssignments(continued) ERRORSOURCESReservedGROUP2Reserved Flash-Double-BitError(uncorrectable)Reserved SRAM-Double-BitError(uncorrectable)ReservedM3Lockup M3ExternalImpreciseAbortReserved CHANNEL28-31 0-34567-15161718-31 3.4InterruptPriority(M3VIM) TheTMS470Mplatforminterruptarchitectureincludesavectoredinterruptmanager(M3VIM)thatprovideshardwareassistanceforprioritizingandcontrollingthemanyinterruptsourcespresentonadevice.Tablemunicatesthedefaultinterruptrequestassignments. MODULES ESMReserved ESMSYSTEM RTIRTIRTIRTIRTIRTIReservedGIOGIOHETHETMibSPI1MibSPI1ReservedLIN/SCI2LIN/SCI2LIN/SCI1LIN/SCI1DCAN1DCAN1ADCADCADC Table3-
4.InterruptRequestAssignments INTERRUPTSOURCES ESMHighlevelinterrupt(NMI)(NMI) ESMLowlevelinterruptSoftwareinterrupt(SSI)pareinterrupt0pareinterrupt1pareinterrupt2pareinterrupt3RTIoverflowinterrupt0RTIoverflowinterrupt1 ReservedGIOInterruptAGIOInterruptBHETlevel0interruptHETlevel1interruptMibSPI1level0interruptMibSPI1level1interrupt ReservedLIN/SCI2level0interruptLIN/SCI2level1InterruptLIN/SCI1level0interruptLIN/SCI1level1InterruptDCAN1level0InterruptDCAN1level1InterruptADCeventgroupinterruptADCswgroup1interruptADCswgroup2interrupt DEFAULTVIMINTERRUPTREQUEST 01234567891011121314151617181920212223242526 22 DeviceConfigurations Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table3-
4.InterruptRequestAssignments(continued) MODULES MibSPI2MibSPI2DCAN2DCAN2 ADCReservedReservedDCAN1DCAN2Reserved INTERRUPTSOURCES MibSPI2level0interruptMibSPI2level1interruptDCAN2level0interruptDCAN2level1interruptADCmagnitudethresholdinterrupt ReservedReservedDCAN1IF3interruptDCAN2IF3interruptReserved DEFAULTVIMINTERRUPTREQUEST 27282930313233343536-47 3.5MibADC Themulti-bufferedanalog-to-digitalconverter(MibADC)eptsananalogsignalandconvertsthesignaltoa10-bitdigitalvalue. TheTMS470MMibADCmodulestoresitsdigitalresultsinoneofthreeFIFObuffers.ThereisoneFIFObufferforeachconversiongroup[event,group1(G1),andgroup2(G2)],andthetotalMibADCFIFOonthedeviceisdividedamongstthesethreeregions.Thesizeoftheindividualgroupbuffersaresoftwareprogrammable.MibADCbufferscanbeservicedbyinterrupts. Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceConfigurations 23 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 3.5.1MibADCEventTriggers Allthreeconversiongroupscanbeconfiguredforevent-triggeredoperation,providinguptothreeeventtriggeredgroups. Thetriggersourceandpolaritycanbeselectedindividuallyforgroup1,group2andtheeventgroupfromtheoptionsidentifiedinTable3-
5. Table3-
5.MibADCEventHookupConfiguration EVENTNO. SOURCESELECTBITSforG1orEVENT(G1SRC[2:0]orEVSRC[2:0]) SIGNALPINNAME
1 000 ADEVT
2 001 HET[1]
3 010 HET[3]
4 011 HET[16]
(1)
5 100 HET[18]
(1)
6 101 HET[24]
(1)
7 110 HET[26]
(1)
8 111 HET[28]
(1)
(1)Thesechannelsareavailableasinternalsignalseveniftheyarenotincludedaspins(节1.1). 3.6MibSPI Themulti-bufferedserialperipheralinterfacemoduleallowsCPUindependentmunicationswithsystemperipherals. TheMibSPI1modulecansupportupto16transfergroupsand8chipselects.Inaddition,upto4dataformatscanbesupportedallowingassignmentofvariousformatstoeachtransfergroup. TheMibSPI2modulecansupportupto8transfergroups,4chipselects,andupto4dataformats. 3.6.1MibSPIEventTrigger TheMibSPImodulehastheabilitytoautomaticallytriggerSPIeventsbasedoninternalandexternaleventtriggers. ThetriggersourcescanbeselectedindividuallyforeachtransfergroupfromtheoptionsidentifiedinTable3-
6. Table3-
6.MibSPI1andMibSPI2EventHookupConfiguration EVENTNO. DisabledEVENT0EVENT1EVENT2EVENT3EVENT4EVENT5EVENT6EVENT7EVENT8 SOURCESELECTBITSFORMIBSPIEVENTS TGXCTRLTRIGSRC[3:0]0000000100100011010001010110011110001001 SIGNALPINNAME NotriggersourceGIOA[0]
(1)GIOA[1]
(1)GIOA[2]
(1)GIOA[3]
(1)GIOA[4]GIOA[5]HET[20]
(1)HET[21]
(1)HET[22]
(1)
(1)Thesechannelsareavailableasinternalsignalseveniftheyarenotincludedaspins(节1.1). 24 DeviceConfigurations Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table3-
6.MibSPI1andMibSPI2EventHookupConfiguration(continued) EVENTNO. EVENT9EVENT10EVENT11EVENT12EVENT13EVENT14 SOURCESELECTBITSFORMIBSPIEVENTS TGXCTRLTRIGSRC[3:0]101010111100110111101111 SIGNALPINNAME HET[23]
(1)HET[28]
(1)HET[29]
(1)HET[30]
(1)HET[31]
(1)InternalTickCounter 3.7JTAGIDThe32-bitJTAGIDcodeforthisdeviceis0x0B8D802F. 3.8ScanChainsThedevicecontainsanICEPICKmoduletoessthedebugscanchains;seeFigure3-
1.Debugscanchain#0handlestheesstotheCPU.TheICEPICKscanIDis0x00366D05,whichisthesameasthedeviceID. TDITDO DAP CPU BoundaryScanChain#
0 ICEPICK BoundaryScan BoundaryScanInterface Figure3-
1.DebugScanChains 3.9AdaptiveImpedance4mAIOBufferTheadaptiveimpedance4mAbufferisabufferthathasbeenexplicitlydesignedtoaddresstheissueofdecouplingEMIsourcesfromthepinswhichtheydrive.Thisisplishedbyadaptivelycontrollingtheimpedanceoftheoutputbufferandshouldbeparticularlyeffectivewithcapacitiveloads.Theadaptiveimpedance4mAbufferfeaturestwomodesofoperation:ImpedanceControlMode,andLow-PowerMode/StandardBufferModeasdefinedbelow:•ImpedanceControlModeisenabledinthedesignbydefault.Thismodeadaptivelycontrolstheimpedanceoftheoutputbuffer. Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceConfigurations 25 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 •StandardBufferModeisusedtoconfigurethebufferbackintoagenericconfiguration.Thisbuffermodeisusedwhenitisnecessarytodrivetheoutputatveryhighspeeds,orwhenEMIreductionisnotaconcern. Table3-
7.AdaptiveImpedance4mABufferModeAvailability MODULEORPINNAMESYS.ECLKSYS.nRST SYS.TDI/TDOSYS.TMSCHETSCI1LIN/SCI2MIBSPI1MibSPI2Reserved MIBADC.ADEVTDCAN1DCAN2GIOA STANDARDBUFFERENABLE(SBEN)
(1)GPREG1.0GPREG1.1 StandardBufferEnabledStandardBufferEnabled GPREG1.2GPREG1.3GPREG1.4GPREG1.5GPREG1.6GPREG1.7GPREG1.8GPREG1.9GPREG1.10GPREG1.11
(1)SBENconfigurationcanbeachievedusingtheGPREGregisterwithinthesystemframe(0xFFFFFFA0). 26 DeviceConfigurations Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedbackProductFolderLinks:TMS470MF04207TMS470MF03107 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 3.9.1StandardBufferEnableRegister(GPREG1) Ageneralpurposeregisterwiththesystemframehasbeenutilizedtocontroltheenablingofstandardbuffermode.ThisregisterisshowninFigure3-2anddescribedinTable3-
8 NOTEIngeneral,alldeviceregistersaredefinedwithintheTRM(SPNU450);however,incaseswheretheregisterdefinitionisdevicespecific,theregisterisdefinedwithinthedevicespecificdatasheet. 31ReservedR-
0 15 12 11 10
9 Reserved GIOA_SBENDCAN2_SBENDCAN1_SBEN R-
0 RW-
0 RW-
0 RW-
0 7
6 5
4 Reserved MibSPI2_SBEN MIBSPI1_SBEN LIN2SCI2_SBEN RW-
0 RW-
0 RW-
0 RW-
0 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
3 LIN1SCI1_SBEN RW-
0 2HET_SBEN RW-
0 1RST_SBEN RW-
0 Figure3-
2.General-PurposeRegister1(GPREG1) 16 8ADC.ADEVT_ SBENRW-0 0ECLK_SBEN RW-
0 Bit31-12 11 10 9 8 76
5 Table3-
8.General-PurposeRegister1(GPREG1)FieldDescriptions FieldReservedGIOA_SBEN DCAN2_SBEN DCAN1_SBEN ADC.ADEVT_SBEN ReservedMibSPI2_SBEN MIBSPI1 Value 01 01 01 01 01 01 DescriptionThesebitsarereserved.Readsreturn0andwriteshavenoeffect.GIOAportstandardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallGIOApinsStandardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.DCAN2standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallDCAN2pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.DCAN1standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallDCAN1pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.ADC.ADEVTstandardbufferenablebit.Thisbitenables/disablesstandardbuffermodefortheADC.ADEVTpin.Standardbuffermodeisnotenabled.StandardbuffermodeisenabledfortheADEVTpin.Thesebitsarereserved.Readsreturn0andwriteshavenoeffect.MibSPI2standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallMibSPI2pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.MIBSPI1standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallMIBSPI1pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins. Copyright©2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback ProductFolderLinks:TMS470MF04207TMS470MF03107 DeviceConfigurations 27 TMS470MF04207TMS470MF03107 ZHCS061C–JANUARY2012 Table3-
8.General-PurposeRegister1(GPREG1)FieldDescriptions(continued) BitField4LIN2SCI2_SBEN3LIN1SCI1_SBEN2HET_SBEN1RST_SBEN0ECLK_SBEN Value 01 01 01 01 01 DescriptionLIN/SCI2standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallLIN/SCI2pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.LIN/SCI1standardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallLIN/SCI1pins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.HETstandardbufferenablebit.Thisbitenables/disablesstandardbuffermodeforallHETpins.Standardbuffermodeisnotenabled.Standardbuffermodeisenabledforallassociatedmodulepins.RSTstandardbufferenablebit.Thisbitenables/disablesstandardbuffermodefortheRSTpin.Standardbuffermodeisnotenabled.StandardbuffermodeisenabledfortheRSTpin.ECLKstandardbufferenablebit.Thisbitenables/disablesstanda
声明：
该资讯来自于互联网网友发布，如有侵犯您的权益请联系我们。
